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Zhaoxin Zhang
Zhaoxin (Shanghai Zhaoxin Semiconductor Co., Ltd.; , ) is a fabless semiconductor company, created in 2013 as a joint venture between VIA Technologies and the Shanghai Municipal Government. The company manufactures x86-compatible desktop and laptop CPUs. The term '' Zhào xīn'' means ''million core''.In China 兆 can mean either short-scale million (1e6) or trillion (1e12). However, for IT-related topics 兆 always means mega/million in mainland China. The processors are created mainly for the Chinese market: the venture is an attempt to reduce the Chinese dependence on foreign technology. Background ''Zhaoxin'' is a joint venture between VIA Technologies and the Shanghai Municipal Government. In 2021 it was reported that VIA has a 14.75% shareholding in the company. China has a domestic policy to "replace all foreign hardware and software from its public infrastructure with homegrown solutions" by 2023 (the so-called 3–5–2 policy). VIA holds an x86 license which allows its ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Shanghai
Shanghai, Shanghainese: , Standard Chinese pronunciation: is a direct-administered municipality and the most populous urban area in China. The city is located on the Chinese shoreline on the southern estuary of the Yangtze River, with the Huangpu River flowing through it. The population of the city proper is the List of largest cities, second largest in the world after Chongqing, with around 24.87 million inhabitants in 2023, while the urban area is the List of cities in China by population, most populous in China, with 29.87 million residents. As of 2022, the Greater Shanghai metropolitan area was estimated to produce a gross metropolitan product (GDP (nominal), nominal) of nearly 13 trillion Renminbi, RMB ($1.9 trillion). Shanghai is one of the world's major centers for finance, #Economy, business and economics, research, science and technology, manufacturing, transportation, List of tourist attractions in Shanghai, tourism, and Culture of Shanghai, culture. The Port of Sh ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Lujiazui
Lujiazui (, ) is a locality in Shanghai, a peninsula formed by a bend in the Huangpu River. Since the early 1990s, Lujiazui has been developed specifically as a new financial district of Shanghai. The decision to earmark Lujiazui for this purpose reflects its location: it is located on the east side of the Huangpu River in Pudong, and sits directly across the river from the old financial and business district of the Bund. Lujiazui is a national-level development zone designated by the government. In 2005, the State Council of the People's Republic of China, State Council reaffirmed the positioning of the Lujiazui area as the only finance and trade zone among the 185 state-level development zones in mainland China. Geography Lujiazui is located in the Pudong New District on the eastern bank of Huangpu River. It forms a peninsula on a bend of the Huangpu River, which turns from flowing north to flowing east. The importance of Lujiazui stems from the fact that it lies directly a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
DirectX
Microsoft DirectX is a collection of application programming interfaces (APIs) for handling tasks related to multimedia, especially game programming and video, on Microsoft platforms. Originally, the names of these APIs all began with "Direct", such as Direct3D, DirectDraw, DirectMusic, DirectPlay, DirectSound, and so forth. The name ''DirectX'' was coined as a shorthand term for all of these APIs (the ''X'' standing in for the particular API names) and soon became the name of the collection. When Microsoft later set out to develop a Video game console, gaming console, the ''X'' was used as the basis of the name Xbox (console), Xbox to indicate that the console was based on DirectX technology. The ''X'' initial has been carried forward in the naming of APIs designed for the Xbox such as DirectInput, XInput and the Cross-platform Audio Creation Tool (XACT), while the DirectX pattern has been continued for Windows APIs such as Direct2D and DirectWrite. Direct3D (the 3D graphics A ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System-on-a-chip
A system on a chip (SoC) is an integrated circuit that combines most or all key components of a computer or electronic system onto a single microchip. Typically, an SoC includes a central processing unit (CPU) with memory, input/output, and data storage control functions, along with optional features like a graphics processing unit (GPU), Wi-Fi connectivity, and radio frequency processing. This high level of integration minimizes the need for separate, discrete components, thereby enhancing power efficiency and simplifying device design. High-performance SoCs are often paired with dedicated memory, such as LPDDR, and flash storage chips, such as eUFS or eMMC, which may be stacked directly on top of the SoC in a package-on-package (PoP) configuration or placed nearby on the motherboard. Some SoCs also operate alongside specialized chips, such as cellular modems. Fundamentally, SoCs integrate one or more processor cores with critical peripherals. This comprehensive integrat ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface. Released to the market in 2014, it is a variant of dynamic random-access memory (DRAM), some of which have been in use since the early 1970s, and a higher-speed successor to the DDR2 and DDR3 technologies. DDR4 is not compatible with any earlier type of random-access memory (RAM) due to different signaling voltage and physical interface, besides other factors. DDR4 SDRAM was released to the public market in Q2 2014, focusing on ECC memory, while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of Haswell-E processors that require DDR4 memory. Features The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higher data rate transfer speeds. The DDR4 standard allows for DIMMs of up t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AES Instruction Set
An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern processors and can greatly accelerate AES operations compared to software implementations. An AES instruction set includes instructions for key expansion, encryption, and decryption using various key sizes (128-bit, 192-bit, and 256-bit). The instruction set is often implemented as a set of instructions that can perform a single round of AES along with a special version for the last round which has a slightly different method. When AES is implemented as an instruction set instead of as software, it can have improved security, as its side channel attack surface is reduced. x86 architecture processors AES-NI (or the Intel Advanced Encryption Standard New Instructions; AES-NI) was the first major implementation. AES-NI is an extension to the x8 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of VIA Eden Microprocessors
The Eden microprocessors from VIA Technologies are fifth- and sixth-generation CPUs targeted at the embedded market. Embedded processors Eden ESP "Samuel 2" (150 nm) * All models support: '' MMX, 3DNow!'' "Nehemiah" (130 nm) * All models support: '' MMX, SSE, VIA PadLock (AES, RNG)'' Eden-N "Nehemiah" (130 nm) * All models support: '' MMX, SSE, VIA PadLock (AES, RNG)'' * VIA PowerSaver supported Eden "Esther" (standard-voltage, 90 nm) * All models support: '' MMX, SSE, SSE2, SSE3, NX bit, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)'' * VIA PowerSaver supported with up to 8 ACPI P-states * Idle power 500 mW "Esther" (ultra-low-voltage, 90 nm) * All models support: '' MMX, SSE, SSE2, SSE3, NX bit, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)'' * VIA PowerSaver supported with up to 8 ACPI P-states Eden X2 "Eden X2" (40 nm) * All models support: '' MMX, SSE, SSE2, SSE3, x86-64, NX bit, x86 virtualization, VIA PadLock (S ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VIA PadLock
VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced Encryption Standard (AES), SHA-1, SHA256, and Montgomery modular multiplication. Instructions The PadLock instruction set can be divided into four subsets: * Random number generation (RNG) ** XSTORE: Store Available Random Bytes (aka XSTORERNG) ** REP XSTORE: Store ECX Random Bytes * Advanced cryptography engine (ACE) - for AES crypto; two versions ** REP XCRYPTECB: Electronic code book ** REP XCRYPTCBC: Cipher Block Chaining ** REP XCRYPTCTR: Counter Mode (ACE2) ** REP XCRYPTCFB: Cipher Feedback Mode ** REP XCRYPTOFB: Output Feedback Mode * SHA hash engine (PHE) ** REP XSHA1: Hash Function SHA-1 ** REP XSHA256: Hash Function SHA-256 * Montgome ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SM4 (cipher)
ShāngMì 4 (SM4, 商密4) (formerly SMS4) is a block cipher, standardised for commercial cryptography in China. It is used in the Chinese National Standard for Wireless LAN WAPI (WLAN Authentication and Privacy Infrastructure), and with Transport Layer Security. SM4 was a cipher proposed for the IEEE 802.11i standard, but it has so far been rejected. One of the reasons for the rejection has been opposition to the WAPI fast-track proposal by the IEEE. SM4 was published as in 2021. The SM4 algorithm was drafted by Data Assurance & Communication Security Center, Chinese Academy of Sciences (CAS), and Commercial Cryptography Testing Center, National Cryptography Administration. It is mainly developed by Lü Shuwang ( zh, 吕述望). The algorithm was declassified in January, 2006, and it became a national standard (GB/T 32907-2016) in August 2016.Lu Shuwang. Journal of Information Security Research, 2016, 2(11): 995-1007. Cipher detail The SM4 cipher has a key size and a blo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SM3 (hash Function)
ShangMi 3 (SM3) is a cryptographic hash function, standardised for use in commercial cryptography in China. It was published by the National Cryptography Administration ( zh, 国家密码管理局) on 2010-12-17 as "GM/T 0004-2012: SM3 cryptographic hash algorithm". SM3 is used for implementing digital signatures, message authentication codes, and pseudorandom number generators. The algorithm is public and is considered similar to SHA-256 in security and efficiency. SM3 is used with Transport Layer Security. Definitive standards SM3 is defined in each of: *GM/T 0004-2012: SM3 cryptographic hash algorithm *GB/T 32905-2016: Information security techniques—SM3 cryptographic hash algorithmWang Xiaoyun. Journal of Information Security Research, 2016, 2(11): 983-994. *ISO/IEC 10118-3:2018—IT Security techniques—Hash-functions—Part 3: Dedicated hash-functions *IETF RFC draft-sca-cfrg-sm3-02 References See also *SM4 (cipher) ShāngMì 4 (SM4, 商密4) (formerly SMS4) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Zhangjiang Hi-Tech Park
The Zhangjiang Hi-Tech Park is a technology park in the Pudong district of Shanghai, China. It is operated by Zhangjiang Hi-Tech Park Development Co., Ltd. The park specializes in research in life sciences, software, semiconductors, and information technology. As of 2009, there were 110 research and development institutions, 3,600 companies and 100,000 workers located in the technology park. In some circles the park is also known as China's Silicon Valley. History The Zhangjiang Hi-Tech Park was established in July 1992. It is situated in the Pudong New Area with a total area of . In 2018, it has bases such as the National Shanghai Biomedical Science and Technology Industry Base, National Information Industry Base, National Integrated Circuit Industry Base, National Semiconductor Lighting Industry Base, National 863 Information Security Fruit Industrialization (Eastern) Base, National Software Industry Base, National Software Export Base, National Cultural Industry Model Base, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of VIA Nano Microprocessors
The Nano microprocessor from VIA Technologies is an eighth-generation CPU targeted at the consumer and embedded market. Desktop and mobile processors Nano L "Nano 2000" series (65nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, x86-64, NX bit, VT-x (stepping 3 and higher), VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver "Nano 3000" series (65nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, x86-64, NX bit, VT-x, VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver "Nano X2" (40nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, x86-64, NX bit, VT-x, VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver * Two Nano 3000 (Isaiah) in the same die "Nano QuadCore" (40nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, x86-64, NX bit, VT-x, VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver * Two Nano x2 (Isaiah) in a Multi-chip module Nano C "Nano QuadCore" (28nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
