Sunny Cove is a

codename A code name, codename, call sign, or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in ...

for a CPU

microarchitecture In electronics, computer science and computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as μarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular ...

developed by

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...

, first released in September 2019. It succeeds the Palm Cove microarchitecture and is fabricated using Intel's 10 nm process node. The microarchitecture is implemented in 10th-generation

Intel Core Intel Core is a line of multi-core (with the exception of Core Solo and Core 2 Solo) central processing units (CPUs) for midrange, embedded, workstation, high-end and enthusiast computer markets marketed by Intel Corporation. These processors ...

processors for mobile (codenamed '' Ice Lake'') and third generation

Xeon Xeon (; ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded markets. It was introduced in June 1998. Xeon processors are based on the same archite ...

scalable server processors (codenamed ''Ice Lake-SP''). 10th-generation Intel Core mobile processors were released in September 2019, while the Xeon server processors were released on April 6, 2021. There are no desktop products featuring Sunny Cove. However, a variant named Cypress Cove is used for the 11th-generation Intel Core desktop processors (codenamed ''

Rocket Lake Rocket Lake is Intel's codename for its 11th generation Core microprocessors. Released on March 30, 2021, it is based on the new Cypress Cove microarchitecture, a variant of Sunny Cove (used by Intel's Ice Lake mobile processors) backporte ...

''). Cypress Cove is a version of the Sunny Cove microarchitecture backported to Intel's 14 nm process node. The direct successor to the Sunny Cove microarchitecture is the Willow Cove microarchitecture, which powers the 11th-generation Intel Core mobile processors.

Features

Sunny Cove was designed by Intel Israel's processor design team in Haifa, Israel. Intel released details of Ice Lake and its microarchitecture, Sunny Cove, during Intel Architecture Day in December 2018, stating that the Sunny Cove cores would be focusing on single-thread performance, new instructions, and scalability improvements. Intel stated that the performance improvements would be achieved by making the core "deeper, wider, and smarter". Sunny Cove features a 50% increase in the size of L1 data cache, a larger L2 cache dependent on product size, larger μOP cache, and larger second-level TLB. The core has also increased in width, by increasing execution ports from eight to ten and by doubling the L1 store bandwidth. Allocation width has also increased from four to five. The 5-level paging scheme supports a linear address space up to 57 bits and a physical address space up to 52 bits, increasing the virtual memory space to 128 petabytes, up from 256 terabytes, and the addressable physical memory to 4 petabytes, up from 64 terabytes.

Improvements

: * On average 18% increase in IPC in comparison to 2015 Skylake running at the same frequency and memory configuration * Increase L1 data cache: 48 kiB (from 32 kiB) * L2 cache: 512 kiB * Larger micro-instruction cache (2304 entries, up from 1536) * Larger

re-order buffer A re-order buffer (ROB) is a hardware unit used in an extension to Tomasulo's algorithm to support out-of-order and speculative instruction execution. The extension forces instructions to be committed in-order. The buffer is a circular buffer ...

(352, up from 224 entries) * Dynamic Tuning 2.0 which allows the CPU to stay at turbo frequencies for longer * Hardware acceleration for SHA operations ( Secure Hash Algorithms) * New

AVX-512 AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and first implemented in the 2016 Intel Xeon Phi x200 (Knights Landing), and then ...

instruction subsets: ** VPOPCNTDQ ** VBMI2 ** BITALG ** VPCLMULQDQ ** GFNI ** VAES ** VNNI * Wider decoder (from skylake's 3 simple + 1 complex 4 way decoding to Sunny cove's 4 simple + 1 complex 5 wide decoder) * 1.6x larger ROB (352, up from 224 entries) ** Scheduler *** 1.65x larger scheduler (160-entry, up from 97 entries) *** Larger dispatch (10-way, up from 8-way) ** 1.55x larger integer register file (280-entry, up from 180) ** 1.33x larger vector register file (224-entry, up from 168) ** Distributed scheduling queues (4 scheduling queues, up from 2) * Intel Deep Learning Boost, used for

machine learning Machine learning (ML) is a field of study in artificial intelligence concerned with the development and study of Computational statistics, statistical algorithms that can learn from data and generalise to unseen data, and thus perform Task ( ...

artificial intelligence Artificial intelligence (AI) is the capability of computer, computational systems to perform tasks typically associated with human intelligence, such as learning, reasoning, problem-solving, perception, and decision-making. It is a field of re ...

inference Inferences are steps in logical reasoning, moving from premises to logical consequences; etymologically, the word '' infer'' means to "carry forward". Inference is theoretically traditionally divided into deduction and induction, a distinct ...

acceleration

Cypress Cove

Cypress Cove is a CPU microarchitecture based on the Sunny Cove microarchitecture designed for 10 nm, backported to 14 nm. It succeeds the Skylake microarchitecture, and is manufactured using Intel's 14 nm process node. Cypress Cove is identical to Sunny Cove, aside from a number of improvements and other changes. Notably the L1 data cache latency has been reduced from five cycles that is on Sunny Cove to just three cycles on Cypress Cove by change from 8 way associativity on Sunny Cove to 12 way associativity On Cypress Cove. Intel claims an increase of 19% in IPC in Cypress Cove–based Rocket Lake processors compared to Comet Lake. Cypress Cove is implemented on 11th Gen Intel Core desktop processors (codenamed ''

''). Rocket Lake and its underlying microarchitecture were first described in November 2020, and was later released on March 30, 2021. SGX is removed from Rocket Lake.

Products

Sunny Cove powers the 10th generation of

mobile processors (codenamed ''Ice Lake'') and the third generation of

Scalable server processors (codenamed ''Ice Lake-SP''). Cypress Cove is implemented on 11th-generation Intel Core desktop processors (codenamed ''Rocket Lake'').

References

{{Intel processor roadmap X86 microarchitectures Intel Intel microarchitectures