Haswell is the
codename
A code name, codename, call sign, or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in ...
for a
processor microarchitecture developed by
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
as the "fourth-generation core" successor to the
Ivy Bridge (which is a
die shrink
The term die shrink (sometimes optical shrink or process shrink) refers to the List of semiconductor scale examples, scaling of metal–oxide–semiconductor (MOS) devices. The act of shrinking a Die (integrated circuit), die creates a somewhat ...
/
tick of the
Sandy Bridge microarchitecture). Intel officially announced
CPUs based on this microarchitecture on June 4, 2013, at
Computex Taipei 2013, while a working Haswell chip was demonstrated at the 2011
Intel Developer Forum. Haswell was the last generation of Intel processor to have socketed processors on mobile. With Haswell, which uses a
22 nm process,
Intel also introduced low-power processors designed for convertible or "hybrid"
ultrabooks, designated by the "U" suffix. Haswell began shipping to manufacturers and
OEMs in mid-2013, with its desktop chips officially launched in September 2013.
Haswell CPUs are used in conjunction with the
Intel 8 Series chipsets,
9 Series chipsets, and
C220 series chipsets.
At least one Haswell-based processor was still being sold in the Pentium G3420.
Windows 7
Windows 7 is a major release of the Windows NT operating system developed by Microsoft. It was Software release life cycle#Release to manufacturing (RTM), released to manufacturing on July 22, 2009, and became generally available on October 22, ...
through
Windows 10
Windows 10 is a major release of Microsoft's Windows NT operating system. The successor to Windows 8.1, it was Software release cycle#Release to manufacturing (RTM), released to manufacturing on July 15, 2015, and later to retail on July 2 ...
were released for the Haswell microarchitecture.
Design
The Haswell architecture is specifically designed to optimize the power savings and performance benefits from the move to
FinFET (non-planar, "3D") transistors on the improved 22 nm process node.
Haswell has been launched in three major forms:
* Desktop version (
LGA 1150 socket and the
LGA 2011-v3 socket): ''Haswell-DT''
* Mobile/Laptop version (
PGA socket): ''Haswell-MB''
*
BGA version:
** 47 W and 57 W
TDP classes: ''Haswell-H'' (for "All-in-one" systems, Mini-ITX form factor motherboards, and other small footprint formats)
** 13.5 W and 15 W TDP classes (
MCP): ''Haswell-ULT'' (for Intel's UltraBook platform)
** 10 W TDP class (SoC): ''Haswell-ULX'' (for tablets and certain UltraBook-class implementations)
Notes
* ULT = ''Ultra Low TDP''; ULX = ''Ultra Low eXtreme'' TDP
* Only certain quad-core variants and BGA R-series
stock keeping unit
In inventory management, a stock keeping unit (abbreviated as SKU, pronounced or ) is the unit of measure in which the stocks of a material are managed. It is a distinct type of item for sale, purchase, or tracking in inventory, such as a produ ...
s (SKUs) receive GT3e (
Intel Iris Pro 5200) integrated graphics. All other models have GT3 (
Intel HD 5000 or
Iris Pro 5100), GT2 (Intel HD 4200, 4400, 4600, P4600 or P4700) or GT1 (Intel HD Graphics) integrated graphics. See also
Intel HD and Iris Graphics for more details.
* Due to the low power requirements of tablet and Ultrabook platforms, Haswell-ULT and Haswell-ULX are only available in dual-core configurations. All other versions come as dual- or quad-core variants.
Performance
Compared to
Ivy Bridge:
* Approximately 8% faster
vector processing
In computing, a vector processor or array processor is a central processing unit (CPU) that implements an instruction set where its Instruction (computer science), instructions are designed to operate efficiently and effectively on large Array d ...
* Up to 5% higher single-threaded performance
* 6% higher multi-threaded performance
* Desktop variants of Haswell draw between 8% and 23% more power under load than Ivy Bridge.
* A 6% increase in sequential CPU
performance
A performance is an act or process of staging or presenting a play, concert, or other form of entertainment. It is also defined as the action or process of carrying out or accomplishing an action, task, or function.
Performance has evolved glo ...
(eight execution ports per core versus six)
* Up to 20% performance increase over the integrated HD4000
GPU (Haswell HD4600 vs Ivy Bridge's built-in
Intel HD4000)
* Total performance improvement on average is about 3%
* Around 15 °C hotter than Ivy Bridge, while clock frequencies of over 4.6 GHz are achievable
Technology
Features carried over from Ivy Bridge
*
22 nm manufacturing process
* 3D
''Tri-Gate'' FinFET transistors
*
Micro-operation cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whic ...
(Uop Cache) capable of storing 1.5 K
micro-operation
In computer central processing units, micro-operations (also known as micro-ops or μops, historically also as micro-actions) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed ma ...
s (approximately 6 KB in size)
* 14- to 19-stage
instruction pipeline
In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming Mac ...
, depending on the micro-operation cache hit or miss (an approach used in the even earlier
Sandy Bridge
Sandy Bridge is the List of Intel codenames, codename for Intel's 32 nm process, 32 nm microarchitecture used in the second generation of the Intel Core, Intel Core processors (Intel Core i7, Core i7, Intel Core i5, i5, Intel Core i3, i3). The Sa ...
microarchitecture)
*Improve OoO window from 168 to 192
*Queue Allocation from 28/threads to 56
* Mainstream variants are up to quad-core.
* Native support for
dual-channel DDR3/DDR3L memory, with up to 32 GB of
RAM on LGA 1150 variants
* 64 KB (32 KB Instruction + 32 KB Data) L1 cache and 256 KB L2 cache per core
* A total of 16
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
3.0 lanes on LGA 1150 variants
New features
CPU
* Wider core: fourth
arithmetic logic unit
In computing, an arithmetic logic unit (ALU) is a Combinational logic, combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on ...
(ALU), third
address generation unit (AGU), second
branch execution unit (BEU), deeper buffers, higher cache bandwidth, improved front-end and
memory controller
A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer's main memory. When a memory controller is integrated into anothe ...
, higher load/store bandwidth.
*
New instructions (HNI, includes
Advanced Vector Extensions 2 (AVX2),
gather,
BMI1, BMI2, ABM and
FMA3
The FMA instruction set is an extension to the 128- and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations. There are two variants:
* FMA4 is supported in AM ...
support).
* The instruction decode queue, which holds instructions after they have been decoded, is no longer statically partitioned between the two threads that each core can service.
* Intel
Transactional Synchronization Extensions (TSX) for the Haswell-EX variant. In August 2014 Intel announced that a bug exists in the TSX implementation on the current
steppings of Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX feature on affected CPUs via a
microcode
In processor design, microcode serves as an intermediary layer situated between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer. It consists of a set of hardware-level instructions ...
update.
*
Fully integrated voltage regulator (FIVR), thereby moving some of the components from
motherboard
A motherboard, also called a mainboard, a system board, a logic board, and informally a mobo (see #Nomenclature, "Nomenclature" section), is the main printed circuit board (PCB) in general-purpose computers and other expandable systems. It ho ...
onto the CPU.
* New advanced power-saving system; due to Haswell's new low-power C6 and C7 sleep states, not all
power supply units (PSUs) are suitable for computers with Haswell CPUs.
* 37, 47, 57 W
thermal design power (TDP) mobile processors.
* 35, 45, 65, 84, 88, 95 and 130–140 W (high-end, Haswell-E) TDP desktop processors.
* 15 W or 11.5W TDP processors for the
Ultrabook platform (multi-chip package like
Westmere) leading to reduced heat, which results in thinner as well as lighter Ultrabooks, but the performance level is slightly lower than the 17 W version.
:
GPU
* Hardware graphics support for
Direct3D 11.1 and
OpenGL
OpenGL (Open Graphics Library) is a Language-independent specification, cross-language, cross-platform application programming interface (API) for rendering 2D computer graphics, 2D and 3D computer graphics, 3D vector graphics. The API is typic ...
4.3.
Intel 10.18.14.5180 driver is the last planned driver release on Windows 7/8.1.
* Four versions of the integrated GPU: GT1, GT2, GT3 and GT3e, where GT3 version has 40 execution units (EUs). Haswell's predecessor, Ivy Bridge, has a maximum of 16 EUs. GT3e version with 40 EUs and on-package 128 MB of embedded DRAM (
eDRAM), called
Crystalwell, is available only in mobile H-
SKUs and desktop (
BGA-only) R-SKUs. Effectively, this eDRAM is a Level 4 cache; it is shared dynamically between the on-die GPU and CPU, and serving as a
victim cache to the CPU's Level 3 cache.
*
HEVC
High Efficiency Video Coding (HEVC), also known as H.265 and MPEG-H Part 2, is a video compression standard designed as part of the MPEG-H project as a successor to the widely used Advanced Video Coding (AVC, H.264, or MPEG-4 Part 10). In co ...
hardware decoding.
I/O
* New sockets and chipsets:
** LGA 1150 for desktops, and rPGA947 and BGA1364 for the mobile market.
**
Z97 (performance) and
H97 (mainstream)
chipset
In a computer system, a chipset is a set of electronic components on one or more integrated circuits that manages the data flow between the processor, memory and peripherals. The chipset is usually found on the motherboard of computers. Chips ...
s for the Haswell Refresh and
Broadwell, in Q2 2014.
**
LGA 2011-v3 with
X99 chipset for the enthusiast-class desktop platform ''Haswell-E''.
*
DDR4 for enterprise/server segments and for the Enthusiast-Class Desktop Platform Haswell-E
* Variable Base clock (BClk) like
LGA 2011
LGA 2011, also called ''Socket R'', is a CPU socket by Intel released on November 14, 2011. It launched along with LGA 1356 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. While LGA 1356 was designed for dual-processor or ...
.
* Optional support for
Thunderbolt technology and Thunderbolt 2.0
* Shrink of the
Platform Controller Hub (PCH), from
65 nm to
32 nm.
Server processors features
*
Haswell-EP
Xeon (; ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, Server (computing), server, and embedded system, embedded markets. It was introduced in June 1998. Xeon proces ...
variant, released in September 2014, with up to 18 cores and marketed as the Xeon E5-1600 v3 and Xeon E5-2600 v3 series.
* Haswell-EX variant, released in May 2015, with 18 cores and functioning TSX.
* A new
cache design.
* Up to 35 MB total unified cache (
last level cache, LLC) for Haswell-EP and up to 40 MB for Haswell-EX.
*
LGA 2011-v3 socket replaces
LGA 2011
LGA 2011, also called ''Socket R'', is a CPU socket by Intel released on November 14, 2011. It launched along with LGA 1356 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. While LGA 1356 was designed for dual-processor or ...
for the Haswell EP; the new socket has the same number of pins, but it is keyed differently due to electrical incompatibility.
* The already launched
Xeon E3 v3 Haswells will get a refresh in spring 2014, together with a refreshed Intel
C220 series PCH chipset.
* TDP up to 160 W for Haswell-EP.
* Haswell-EP models with ten and more cores support ''cluster on die'' (COD) operation mode, allowing CPU's multiple columns of cores and
last level cache (LLC) slices to be logically divided into what is presented as two
non-uniform memory access (NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, therefore decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.
Haswell Refresh
Around the middle of 2014, Intel released a refresh of Haswell, simply titled ''Haswell Refresh''. When compared to the original Haswell CPUs lineup, Haswell Refresh CPUs offer a modest increase in clock frequencies, usually of 100 MHz. Haswell Refresh CPUs are supported by Intel's ''9 Series'' chipsets (Z97 and H97, codenamed
Wildcat Point), while motherboards with ''8 Series'' chipsets (codenamed
Lynx Point) usually require a BIOS update to support Haswell Refresh CPUs.
The CPUs codenamed ''Devil's Canyon'', covering the i5 and i7 K-series
SKUs, employ a new and improved
thermal interface material (TIM) called next-generation polymer thermal interface material (''NGPTIM''). This improved TIM reduces the CPU's operating temperatures and improves the overclocking potential, as something that had been problematic since the introduction of Ivy Bridge. Other changes for the Devil's Canyon CPUs include a TDP increase to 88 W, additional decoupling capacitors to help smooth out the outputs from the fully integrated voltage regulator (FIVR), and support for the
VT-d that was previously limited to non-K-series SKUs.
TSX was another feature brought over from the non-K-series SKUs, until August 2014 when a microcode update disabled TSX due to a bug that was discovered in its implementation.
Windows XP and Vista support
While
Ivy Bridge is the last Intel processor to fully support all versions of Windows XP, Haswell includes limited driver support for certain XP editions such as POSReady2009. People have modified the graphics driver for these versions to adapt to normal Windows XP to varying degrees of success.
Windows Vista support is also dropped with this processor as well. People who have installed x64 version of Vista have reported various problems such as services not starting automatically. The KB4493471 update (officially intended only for
Windows Server 2008, but can be installed on Vista) contains a HAL driver that allegedly fixes these issues; however, upon several tests it's been confirmed - it doesn't fix any of the issues. Windows XP and earlier, and all x86 versions and editions of Vista are unaffected by this bug.
List of Haswell processors
Desktop processors

* All models support: ''
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4.1,
SSE4.2,
F16C, Enhanced Intel
SpeedStep Technology (EIST),
Intel 64, XD bit (an
NX bit implementation),
Intel VT-x,'' and ''
Smart Cache.''
** Core i3, i5 and i7 support ''
AVX,
AVX2
Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then Sandy Bridge New Instructions) are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They w ...
,
BMI1,
BMI2,
FMA3
The FMA instruction set is an extension to the 128- and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations. There are two variants:
* FMA4 is supported in AM ...
,'' and ''
AES-NI.''
** Core i3 and i7, as well as the Core i5-4570T and i5-4570TE, support ''
Hyper-Threading (HT)''.
** Core i5 and i7 support ''
Turbo Boost 2.0.''
** Although it was initially supported on selected models, since August 2014 desktop variants no longer support ''
TSX'' due to a bug that was discovered in its implementation; as a workaround, a microcode update disabled the TSX feature.
** SKUs below 45xx as well as R-series and K-series SKUs do not support ''
Trusted Execution Technology'' or ''
vPro.''
** ''
Intel VT-d'', which is Intel's
IOMMU, is supported on all i5 and i7 SKUs except the i5-4670K and i7-4770K.
Support for VT-d requires the chipset and motherboard to also support VT-d.
** Models i5-4690K and i7-4790K, codenamed Devil's Canyon, have a better internal
thermal grease to help heat escape and an improved internal
voltage regulator
A voltage regulator is a system designed to automatically maintain a constant voltage. It may use a simple feed-forward design or may include negative feedback. It may use an electromechanical mechanism or electronic components. Depending on the ...
("FIVR"), to help deliver cleaner power in situations like overclocking.
* Transistors: 1.4 billion
*
Die size: 177 mm
2
*
Intel HD and Iris Graphics in following variants:
** R-series desktop processors feature Intel Iris Pro 5200 graphics (GT3e).
** The i3-41xxx processors include HD 4400 graphics (GT2).
** All other i3, i5 and i7 desktop processors include Intel HD 4600 graphics (GT2).
** Celeron and Pentium processors contain Intel HD Graphics (GT1).
* Pentium G3258, also known as the ''Pentium Anniversary Edition'', has an unlocked multiplier. Its release marks 20 years of "Pentium" as a brand.
The following table lists available desktop processors.
: Some of these configurations could be disabled by the chipset. For example, H-series chipsets disable all PCIe 3.0 lane configurations except 1×16.
: This feature also requires a chipset that supports VT-d like the Q87 chipset or the X99 chipset.
: This is called ''20th Anniversary Edition'' and has an unlocked multiplier.
SKU suffixes to denote:
* K unlocked
(adjustable CPU multiplier up to 63x)
**The Pentium G3258 CPU is unlocked despite not having the K-suffix.
* S performance-optimized lifestyle
(low power with 65 W TDP)
* T power-optimized lifestyle
(ultra low power with 35–45 W TDP)
* R BGA packaging / High-performance GPU
(Iris Pro 5200 (GT3e))
* X extreme edition
(adjustable CPU ratio with no ratio limit)
Server processors
* All models support: ''
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4.1,
SSE4.2,
AVX (Advanced Vector Extensions),
AVX2
Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then Sandy Bridge New Instructions) are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They w ...
,
FMA3
The FMA instruction set is an extension to the 128- and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations. There are two variants:
* FMA4 is supported in AM ...
,
F16C, BMI (Bit Manipulation Instructions 1)+BMI2, Enhanced Intel
SpeedStep Technology (EIST),
Intel 64, XD bit (an
NX bit implementation),
TXT,
Intel vPro,
Intel VT-x,
Intel VT-d,
hyper-threading (except E3-1220 v3 and E3-1225 v3),
Turbo Boost 2.0,
AES-NI'', and ''Smart Cache.''
* Haswell-EX models (E7-48xx/88xx v3) support ''
TSX'', while for Haswell-E, Haswell-WS (E3-12xx v3) and Haswell-EP (E5-16xx/26xx v3) models it was disabled via a microcode update in August 2014, due to a bug that was discovered in the TSX implementation.
* Transistors: 5.56 billion
* Die size: 661 mm
2
The first digit of the model number designates the largest supported multi-socket configuration; thus, E5-26xx v3 models support up to dual-socket configurations, while the E7-48xx v3 and E7-88xx v3 models support up to quad- and eight-socket configurations, respectively. Also, E5-16xx/26xx v3 and E7-48xx/88xx v3 models have no integrated GPU.
Lists of launched server processors are below, split between Haswell E3-12xx v3, E5-16xx/26xx v3 and E7-48xx/88xx v3 models.
SKU suffixes to denote:
* L low power
Mobile processors
* All models support: ''
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4.1,
SSE4.2, F16C, Enhanced Intel
SpeedStep Technology (EIST),
Intel VT-x,
Intel 64, XD bit (an
NX bit implementation)'', and ''Smart Cache.''
** Core i3, i5 and i7 support ''
AVX,
AVX2
Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then Sandy Bridge New Instructions) are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They w ...
, BMI1, BMI2,
FMA3
The FMA instruction set is an extension to the 128- and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations. There are two variants:
* FMA4 is supported in AM ...
'', and ''
hyper-threading (HT)''.
** Core i3, i5 and i7 except the Core i3-4000M support ''
AES-NI''.
** Core i5 and i7 except the Core i5-4410E, i5-4402EC, i7-4700EC, and i7-4702EC support ''
Turbo Boost 2.0.''
* Haswell-ULT and ULX: Platform Controller Hub (PCH) integrated into the CPU package, slightly reducing the amount of space used on motherboards.
* Transistors: 1.3 billion
* Die size: 181 mm
2
The following table lists available mobile processors.
- When a cooler or quieter mode of operation is desired, this mode specifies a lower TDP and lower guaranteed frequency versus the nominal mode.
- This is the processor's rated frequency and TDP.
- When extra cooling is available, this mode specifies a higher TDP and higher guaranteed frequency versus the nominal mode.
SKU suffixes to denote:
* M dual-core mobile (
Socket G3)
* MQ quad-core mobile (
Socket G3)
* U ultra-low power (BGA1168 packaging)
* MX quad-core extreme mobile (
Socket G3)
* Y extreme low-power (BGA1168 packaging)
* H dual-core BGA1364 packaging
* HQ quad-core BGA1364 packaging
* E embedded version of H
* EQ embedded version of HQ
See also
*
LGA 1150: Original Haswell chipsets
*
List of Intel chipsets
*
List of Intel CPU microarchitectures
Notes
References
External links
*
*
*
*
*
*
{{DEFAULTSORT:Haswell (microarchitecture)
Haswell microarchitecture
Intel microarchitectures
Transactional memory
X86 microarchitectures
Computer-related introductions in 2013