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Platform Controller Hub
The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chipsa northbridge and southbridge, and first appeared in the Intel 5 Series. The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a chipset since the release of the Zen architecture in 2017. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel 5 Series Architecture
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and incorporated in Delaware. Intel designs, manufactures, and sells computer components such as central processing units (CPUs) and related products for business and consumer markets. It is one of the world's largest semiconductor chip manufacturers by revenue, and ranked in the ''Fortune'' 500 list of the largest United States corporations by revenue for nearly a decade, from 2007 to 2016 fiscal years, until it was removed from the ranking in 2018. In 2020, it was reinstated and ranked 45th, being the 7th-largest technology company in the ranking. It was one of the first companies listed on Nasdaq. Intel supplies microprocessors for most manufacturers of computer systems, and is one of the developers of the x86 series of instruction sets found in most personal computers (PCs). It also manufactures chipsets, network interface controllers, flash mem ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Front-side Bus
The front-side bus (FSB) is a computer communication interface ( bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge. Depending on the implementation, some computers may also have a back-side bus that connects the CPU to the cache. This bus and the cache connected to it are faster than accessing the system memory (or RAM) via the front-side bus. The speed of the front side bus is often used as an important measure of the performance of a computer. The original front-side bus architecture was replaced by HyperTransport, Intel QuickPath Interconnect, and Direct Media Interface, followed by Intel Ultra Path Interconnect and AMD's Infinity Fabric. History The term came into use by Intel Corporation about the time the Pentium Pro and Pentium II products were announ ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
I²C
I2C (Inter-Integrated Circuit; pronounced as "" or ""), alternatively known as I2C and IIC, is a synchronous, multi-master/multi-slave, single-ended, serial communication bus invented in 1980 by Philips Semiconductors (now NXP Semiconductors). It is widely used for attaching lower-speed peripheral integrated circuits (ICs) to processors and microcontrollers in short-distance, intra-board communication. The I2C bus can be found in a wide range of electronics applications where simplicity and low manufacturing cost are more important than speed. PC components and systems which involve I2C include serial presence detect (SPD) EEPROMs on dual in-line memory modules (DIMMs) and Extended Display Identification Data (EDID) for monitors via VGA, DVI, and HDMI connectors. Common I2C applications include reading hardware monitors, sensors, real-time clocks, controlling actuators, accessing low-speed DACs and ADCs, controlling simple LCD or OLED displays, changing computer ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel High Definition Audio
Intel High Definition Audio (IHDA) (also called HD Audio or development codename Azalia) is a specification for the audio sub-system of personal computers. It was released by Intel in 2004 as the successor to their AC'97 PC audio standard, but it is not backwards-compatible with it. Features The Intel High Definition Audio specification includes the following features: * Up to 15 input and 15 output streams * Up to 16 PCM audio channels per stream * Sample resolutions of 8–32 bits * Sample rates of 6–192 kHz * Support for audio codecs (e.g., ADC, DAC), modem codecs, and vendor-offered codecs * Discoverable codec architecture * Fine-grained codec power-control * Audio jack detection, sensing, and retasking * Vendor-offered (OEM or IHV) audio enhancement features Motherboards typically do not have any more than eight built-in output channels (7.1 surround sound) and four input channels (back and front panel microphone inputs, and a back-panel stereo line-in). Users ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System In Package
A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate. The SiP performs all or most of the functions of an electronic system, and is typically used when Integrated circuit design, designing components for mobile phone, mobile phones, Portable media player, digital music players, etc. die (integrated circuit), Dies containing integrated circuits may be stacked vertically on the package substrate. They are internally connected by fine wires that are bonded to the package substrate. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together and to the package substrate, or even both techniques can be used in a single package. SiPs are like system on a c ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Skylake (microarchitecture)
Skylake is Intel's codename for its sixth generation Core microprocessor family that was launched on August 5, 2015, succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology as its predecessor, serving as a tock in Intel's tick–tock manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Whiskey Lake, and Comet Lake CPUs. Skylake is the last Intel platform on which Windows earlier than Windows 10 are officially supported by Microsoft, although enthusiast-created modifications are available that disabled the Windows Update check and allowed Windows 8.1 and earlier to continue to receive Windows Updates on this and later platforms. Some of the processors based on the Skylake microarchitecture are marketed as sixth-generation Core. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Haswell (microarchitecture)
Haswell is the List of Intel codenames, codename for a Central processing unit, processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge (microarchitecture), Ivy Bridge (which is a die shrink/Tick–tock model, tick of the Sandy Bridge, Sandy Bridge microarchitecture). Intel officially announced CPUs based on this microarchitecture on June 4, 2013, at Computex Taipei 2013, while a working Haswell chip was demonstrated at the 2011 Intel Developer Forum. Haswell was the last generation of Intel processor to have socketed processors on mobile. With Haswell, which uses a 22 nm process, Intel also introduced low-power processors designed for convertible or "hybrid" ultrabooks, designated by the "U" suffix. Haswell began shipping to manufacturers and Original equipment manufacturer, OEMs in mid-2013, with its desktop chips officially launched in September 2013. Haswell CPUs are used in conjunction with the Intel 8 Series chipsets, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cannon Lake (microarchitecture)
Cannon Lake is list of Intel codenames, Intel's codename for the ninth generation of Intel Core, Core processors based on Palm Cove, a 10 nm process, 10 nm die shrink of the Kaby Lake microarchitecture. As a die shrink, Palm Cove is a new ''process'' in Intel's Process–architecture–optimization model, process-architecture-optimization execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the AVX-512 instruction set. Prior to Cannon Lake's launch, Intel launched another 14 nm process refinement with the codename Coffee Lake. The successor of Cannon Lake is Ice Lake (microarchitecture), Ice Lake, powered by the Sunny Cove (microarchitecture), Sunny Cove microarchitecture, which represents the ''architecture'' phase in the ''process-architecture-optimization'' model. Design history and features Cannon Lake was initially expected to be released in 2015/2016, but the release was pushed back to 2018. Inte ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nonvolatile BIOS Memory
Nonvolatile BIOS memory refers to a small Memory (computers), memory on personal computer, PC motherboards that is used to store BIOS settings. It is traditionally called CMOS RAM because it uses a volatile memory, volatile, low-power CMOS, complementary metal–oxide–semiconductor (CMOS) Static random access memory, SRAM (such as the Motorola MC146818 or similar) powered by a small battery when system and standby power is off. It is referred to as non-volatile memory or Non-volatile random-access memory, NVRAM because, after the system loses power, it does retain state by virtue of the CMOS battery. When the battery fails, BIOS settings are reset to their defaults. The battery can also be used to power a real time clock (RTC) and the RTC, NVRAM and battery may be integrated into a single component. The name CMOS memory comes from the technology used to make the memory, which is easier to say than NVRAM. The CMOS RAM and the real-time clock have been integrated as a part of t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nehalem (microarchitecture)
Nehalem is the codename for Intel's 45 nm microarchitecture released in November 2008. It was used in the first generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The term "Nehalem" comes from the Nehalem River. Nehalem is built on the 45 nm process, is able to run at higher clock speeds without sacrificing efficiency, and is more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem is an architecture that differs radically from NetBurst, while retaining some of the latter's minor features. Nehalem later received a die-shrink to 32 nm with Westmere, and was fully succeeded by "second-generation" Sandy Bridge in January 2011. Technology * Cache line block on L2/L3 cache was reduced from 128 bytes in NetBurst & Merom/Penryn to 64 bytes per line in this gene ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel Management Engine
The Intel Management Engine (ME), also known as the Intel Manageability Engine, is an autonomous subsystem that has been incorporated in virtually all of Intel's processor chipsets since 2008. It is located in the Platform Controller Hub of modern Intel motherboards. The Intel Management Engine always runs as long as the motherboard is receiving power, even when the computer is turned off. This issue can be mitigated with the deployment of a hardware device which is able to disconnect all connections to mains power as well as all internal forms of energy storage. The Electronic Frontier Foundation and some security researchers have voiced concern that the Management Engine is a backdoor. Intel's main competitor, AMD, has incorporated the equivalent AMD Secure Technology (formally called Platform Security Processor) in virtually all of its post-2013 CPUs. Difference from Intel AMT The Management Engine is often confused with Intel AMT (Intel Active Management Technology) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Uncore
"Uncore" is a term used by Intel to describe the functions of a microprocessor that are not in the core, but which must be closely connected to the core to achieve high performance. It has been called "system agent" since the release of the Sandy Bridge microarchitecture. Details Typical processor cores contains the components of the processor involved in executing instructions, including the ALU, FPU, L1 and L2 cache. In contrast, Uncore functions include QPI controllers, L3 cache, snoop agent pipeline, on-die memory controller, on-die PCI Express Root Complex, and Thunderbolt controller. Other bus controllers such as SPI and LPC are part of the chipset. The Intel uncore design stems from its origin as the northbridge. The design of the Intel uncore reorganizes the functions critical to the core, making them physically closer to the core on-die, thereby reducing their access latency. Specifically, the microarchitecture In electronics, computer science and com ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
