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45nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame. Matsushita and Intel started mass-producing 45 nm chips in late 2007, and AMD started production of 45 nm chips in late 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008, SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM. In 2008, TSMC moved on to a 40nm process. Many critical feature sizes are smaller than the wavelength of light used for lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Double Patterning
Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary. Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by Intel for line-cutting at its 45nm node or TSMC at its 28nm node. Even for electron-beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning. Double patterning lithography was first demonstrated in 1983 by D. C. Flanders and N. N. Efremow. Since then several double patterning te ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MOSFET
upright=1.3, Two power MOSFETs in amperes">A in the ''on'' state, dissipating up to about 100 watt">W and controlling a load of over 2000 W. A matchstick is pictured for scale. In electronics, the metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, MOS FET, or MOS transistor) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The term ''metal–insulator–semiconductor field-effect transistor'' (''MISFET'') is almost synonymous with ''MOSFET''. Another near-synonym is ''insulated-gate field-effect transistor'' (''IGFET''). The main advantage of a MOSFET is that it requires almost no input current to control the load current under steady-state or low-frequency conditions ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
High-κ Dielectric
In the semiconductor industry, the term high-κ dielectric refers to a material with a high dielectric constant (κ, kappa), as compared to silicon dioxide. High-κ dielectrics are used in semiconductor manufacturing processes where they are usually used to replace a silicon dioxide gate dielectric or another dielectric layer of a device. The implementation of high-κ gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components, colloquially referred to as extending Moore's Law. Sometimes these materials are called "high-k" (pronounced "high kay"), instead of "high-κ" (high kappa). Need for high-κ materials Silicon dioxide () has been used as a gate oxide material for decades. As metal–oxide–semiconductor field-effect transistors (MOSFETs) have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance (per unit area) and thereby drive current (per ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation , Intel. more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in , in the presentation. SSE4 extended the SSE3 instruction set which was released in early 2004. All software using previous Intel SIMD instructio ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Semiconductor Node
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as microprocessors, microcontrollers, and memories (such as RAM and flash memory). It is a multiple-step photolithographic and physico-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications. This article focuses on the manufacture of integrated circuits, however steps such as etching and photolithography can be used to manufacture other devices such as LCD and OLED displays. The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs", with the central part being the " clean room". In more advanced ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Advanced Micro Devices
Advanced Micro Devices, Inc. (AMD) is an American multinational corporation and technology company headquartered in Santa Clara, California and maintains significant operations in Austin, Texas. AMD is a Information technology, hardware and Fabless manufacturing, fabless company that designs and develops List of AMD processors, central processing units (CPUs), List of AMD graphics processing units, graphics processing units (GPUs), field-programmable gate arrays (FPGAs), System on a chip, system-on-chip (SoC), and high-performance computing, high-performance computer solutions. AMD serves a wide range of business and consumer markets, including gaming, data centers, artificial intelligence (AI), and embedded systems. AMD's main products include List of AMD microprocessors, microprocessors, motherboard chipsets, embedded processors, and List of AMD graphics processing units, graphics processors for Server (computing), servers, workstations, personal computers, and embedded syst ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
32 Nm Process
The "32 nm" node is the step following the "45 nm" process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level. Toshiba produced commercial 32 GiB NAND flash memory chips with the "32nm" process in 2009. Intel and AMD produced commercial microchips using the "32 nm" process in the early 2010s. IBM and the Common Platform also developed a "32 nm" high-κ metal gate process. Intel began selling its first "32 nm" processors using the Westmere architecture on 7 January 2010. Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, nor metal pitch, nor gate pitch on a "32nm" device is thirty-two nanometers. The "28 nm" node is an intermediate half-node die shrink based on the "32 nm" process. The "32 nm" process ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Low-κ Dielectric
In semiconductor manufacturing, a low-κ is a material with a small relative dielectric constant (κ, kappa) relative to silicon dioxide. Low-κ dielectric material implementation is one of several strategies used to allow continued scaling of microelectronic devices, colloquially referred to as extending Moore's law. In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build up and crosstalk adversely affect the performance of the device. Replacing the silicon dioxide with a low-κ dielectric of the same thickness reduces parasitic capacitance, enabling faster switching speeds (in case of synchronous circuits) and lower heat dissipation. In conversation such materials may be referred to as "low-k" (spoken "low-kay") rather than "low-κ" (low-kappa). Low-κ materials ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Samsung Electronics
Samsung Electronics Co., Ltd. (SEC; stylized as SΛMSUNG; ) is a South Korean multinational major appliance and consumer electronics corporation founded on 13 January 1969 and headquartered in Yeongtong District, Suwon, South Korea. It is currently the pinnacle of the Samsung ''chaebol'', accounting for 70% of the group's revenue in 2012, and has played a key role in the group's corporate governance due to cross ownership. It is majority-owned by foreign investors. Samsung Electronics is the world's List of largest technology companies by revenue, second-largest technology company by revenue, and its market capitalization stood at US$520.65 billion, the 12th largest in the world. It became the world's largest manufacturer of smartphones in 2024. Samsung is known most notably for its Samsung Galaxy brand consisting of phones such as its flagship Samsung Galaxy S series, Galaxy S series, popular midrange Samsung Galaxy A series, Galaxy A series as well as the premium Samsu ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
14 Nm Process
The "14 nanometer process" refers to a marketing term for the MOSFET technology node that is the successor to the "22nm" (or "20nm") node. The "14nm" was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following "22nm" was expected to be "16nm". All "14nm" nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a "14nm" device is fourteen nanometers. For example, TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density, and TSMC's " 7 nm" processes are dimensionally similar to Intel's "10 nm" process. Samsung Electronics taped out a "14 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
22 Nm Process
The "22 nm" node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. It was first demonstrated by semiconductor companies for use in RAM in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012 with the Intel Ivy Bridge processors. Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a "22nm" device is twenty-two nanometers. The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Immersion Lithography
Immersion lithography is a technique used in semiconductor manufacturing to enhance the resolution and accuracy of the lithographic process. It involves using a liquid medium, typically water, between the lens and the wafer during exposure. By using a liquid with a higher refractive index than air, immersion lithography allows for smaller features to be created on the wafer. Immersion lithography replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The angular resolution is increased by a factor equal to the refractive index of the liquid. Current immersion lithography tools use highly purified water for this liquid, achieving feature sizes below 45 nanometers. Background The ability to resolve features in optical lithography is directly related to the numerical aperture of the imaging equipment, the numerical aperture being the sine of the maximum refraction angle multiplied by the refracti ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
