The Wishbone Bus is an

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intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project. Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels. This ambiguity is intentional. Wishbone is made to let designers combine several designs written in

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or some other logic-description language for

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(EDA). Wishbone provides a standard way for designers to combine these hardware logic designs (called "cores"). Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags. Wishbone is

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. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of

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, to prove its concepts are in the public domain. A device does not ''conform'' to the Wishbone specification unless it includes a ''data sheet'' that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others. The Simple Bus Architecture is a simplified version of the Wishbone specification."About SBA"

Wishbone topologies

Wishbone adapts well to common topologies such as point-to-point, many-to-many (i.e. the classic bus system), hierarchical, or even switched fabrics such as

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es. In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.

Shared bus

image:wishbone_shared_bus.jpg

Data flow

image:wishbone_pipeline.jpg

Crossbar switch

image:wishbone_cross_bar.jpg

Comparisons

Wishbone control signals compared to other system on a chip (SoC) bus standards:

References

External links

Wishbone Version B3
The PDF specification
Wishbone Version B4
PDF specification of latest version of Wishbone
appnote_01
Combining WISHBONE interface signals application note
Comparison to other SoC buses

Wishbone@OpenCores

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