TILE64 is a

VLIW Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to ex ...

ISA

multicore processor A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such ...

manufactured by Tilera. It consists of a

mesh network A mesh network is a local area network topology in which the infrastructure nodes (i.e. bridges, switches, and other infrastructure devices) connect directly, dynamically and non-hierarchically to as many other nodes as possible and cooperate wit ...

of 64 "tiles", where each tile houses a general purpose processor,

cache Cache, caching, or caché may refer to: Places United States * Cache, Idaho, an unincorporated community * Cache, Illinois, an unincorporated community * Cache, Oklahoma, a city in Comanche County * Cache, Utah, Cache County, Utah * Cache Coun ...

, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short- pipeline, in-order, three-issue cores implement a MIPS-inspired

instruction set In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called a ...

. Each core has a register file and three functional units: two integer

arithmetic logic unit In computing, an arithmetic logic unit (ALU) is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point numb ...

s and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE64 has four DDR2 controllers, two 10-gigabit

Ethernet Ethernet () is a family of wired computer networking technologies commonly used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN). It was commercially introduced in 1980 and first standardized in ...

interfaces, two four-lane

PCIe PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...

interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz. According to CTO and co-founder

Anant Agarwal Anant Agarwal is an Indian computer architecture researcher. He is a professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (MIT), where he led the development of Alewife, an early cache cohe ...

, Tilera will target the chip at networking equipment and digital video markets where the demands for computing processing are high. Support for the TILE64 architecture was added to

Linux kernel The Linux kernel is a free and open-source, monolithic, modular, multitasking, Unix-like operating system kernel. It was originally authored in 1991 by Linus Torvalds for his i386-based PC, and it was soon adopted as the kernel for the GNU ...

version 2.6.36 but was dropped in kernel version 4.16. A non-official LLVM back-end for Tilera exists.Tilera TILE64 Back-End For LLVM Published
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Phoronix Phoronix Test Suite (PTS) is a free and open-source benchmark software for Linux and other operating systems which is developed by Michael Larabel and Matthew Tippett. The Phoronix Test Suite has been endorsed by sites such as Linux.com, Lin ...

, September 6, 2012

References

External links

Tilera website

MIT startup raises multicore bar with new 64-core CPU
* {{webarchive , date=2013-01-19 , url=https://archive.today/20130119201711/http://news.com.com/Chipmakers+aim+to+unclog+data+paths/2100-1006_3-6203218.html , title=Chipmakers aim to unclog data paths Manycore processors Very long instruction word computing Computer-related introductions in 2007