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The Intel Atom is Intel's line of low-power, low-cost and low-performance x86 and x86-64 microprocessors. Atom, with codenames of ''
Silverthorne The Town of Silverthorne is a home rule municipality in Summit County, Colorado. According to the 2010 Census, the population of the city is 3,887. History The town was named for Judge Marshall Silverthorn who served as the judge of the mine ...
'' and '' Diamondville'', was first announced on March 2, 2008. For Nettop and Netbook Atom Microprocessors after ''Diamondville'', the memory and graphics controller are moved from the northbridge to the CPU. This explains the drastically increased transistor count for post-''Diamondville'' Atom microprocessors.


Nettop processors (small desktop)


Bonnell microarchitecture


" Diamondville" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Hyper-Threading * Transistors: 47 million * Die size: 25.96 mm² (3.27 × 7.94) * Package size: 22 mm × 22 mm


" Pineview" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Hyper-Threading * Integrated
GMA 3150 The Intel Graphics Media Accelerator (GMA) is a series of integrated graphics processors introduced in 2004 by Intel, replacing the earlier Intel Extreme Graphics series and being succeeded by the Intel HD and Iris Graphics series. This series t ...
GPU and DDR3/DDR2 single-channel memory controller * Transistors: 123 million (single-core), 176 million (dual-core) * Die size: 66 mm² (9.56 × 6.89) (single-core), 87 mm² (9.56 × 9.06) (dual core) * Package size: 22 mm × 22 mm


" Cedarview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Hyper-Threading (D2550, D2560, D2700, D2701 only) * Integrated PowerVR SGX545-based Intel GMA 3600/ GMA 3650 GPU and DDR3 single-channel memory controllerhttps://www.intel.ca/content/dam/doc/datasheet/atom-d2000-n2000-vol-1-datasheet.pdf * Package size: 22 mm × 22 mm


Netbook Netbook was a commonly used term that identified a product class of small and inexpensive laptops which were sold from 2007 to around 2013. These machines were designed primarily as cost-effective tools for consumers to access the Inte ...
processors (sub-notebook)


Bonnell microarchitecture


" Diamondville" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Hyper-Threading * Transistors: 47 million * Die size: 26 mm² * Package size: 22 mm × 22 mm


" Pineview" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Hyper-Threading * Integrated
GMA 3150 The Intel Graphics Media Accelerator (GMA) is a series of integrated graphics processors introduced in 2004 by Intel, replacing the earlier Intel Extreme Graphics series and being succeeded by the Intel HD and Iris Graphics series. This series t ...
GPU and DDR3/DDR2 single-channel memory controller supporting up to 2 GB * Transistors: 123 million (single-core), 176 million (dual-core) * Die size: 66 mm² (9.56 × 6.89) (single-core), 87 mm² (9.56 × 9.06) (dual core) * Package size: 22 mm × 22 mm


" Cedarview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Hyper-Threading * Integrated PowerVR SGX545-based Intel GMA 3600/ GMA 3650 GPU and DDR3 single-channel memory controller * Package size: 22 × 22 mm


MID processors/SoCs ( UMPC/ Smartphone/

IoT The Internet of things (IoT) describes physical objects (or groups of such objects) with sensors, processing ability, software and other technologies that connect and exchange data with other devices and systems over the Internet or other com ...
)


Bonnell microarchitecture


"

Silverthorne The Town of Silverthorne is a home rule municipality in Summit County, Colorado. According to the 2010 Census, the population of the city is 3,887. History The town was named for Judge Marshall Silverthorn who served as the judge of the mine ...
" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Hyper-Threading * Models Z520, Z520PT, Z530, Z530P, Z540, Z550 and Z560 support Intel VT-x * Model Z515 supports ''Intel Burst Performance Technology'' * Uses the
Poulsbo Poulsbo ( ) is a city on Liberty Bay in Kitsap County, Washington, United States. It is the smallest of the four cities in Kitsap County. The population was 9,200 at the 2010 census and an estimated 10,927 in 2018. The area was historically in ...
chipset. * Transistors: 47 million * Die size: 26 mm² * Package size: 13 mm × 14 mm / 22 mm × 22 mm (processors ending with the ''P'' or ''PT'' sSpec number)


" Lincroft" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Hyper-Threading. All except Z605 support Intel Burst Performance Technology (BPT). * GMA 600 GPU and DDR2 single-channel memory controller are integrated into the processor.https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z6xx-datasheet.pdf * Transistors: 140 million * Die size: 7.34 mm × 8.89 mm = 65.2526 mm² * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings: C0


" Penwell" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Intel Burst Performance Technology (BPT), Hyper-Threading. * Integrated PowerVR SGX540 GPU and DDR3 single-channel memory controller * Package size: 12 mm × 12 × 1.0 mm


Silvermont microarchitecture


" Merrifield" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI, Intel Burst Performance Technology (BPT). * Z3480 also supports
Intel Wireless Display Wireless Display (WiDi) is technology developed by Intel that enables users to stream music, movies, photos, videos and apps without wires from a compatible computer to a compatible HDTV or through the use of an adapter with other HDTVs or mon ...
. * Integrated PowerVR G6400 GPU, memory controller supporting two 32-bit LPDDR3 channels up to 4 GB, USB 3.0 controller, eMMC 4.5 * Paired with Intel XMM 7160 LTE modem supporting 4G/3G/2G * Package size: 12 mm × 12 × 1.0 mm


" Moorefield" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI, Intel Burst Performance Technology (BPT),
Intel Wireless Display Wireless Display (WiDi) is technology developed by Intel that enables users to stream music, movies, photos, videos and apps without wires from a compatible computer to a compatible HDTV or through the use of an adapter with other HDTVs or mon ...
. * GPU (
PowerVR PowerVR is a division of Imagination Technologies (formerly VideoLogic) that develops hardware and software for 2D and 3D rendering, and for video encoding, decoding, associated image processing and DirectX, OpenGL ES, OpenVG, and OpenCL accelera ...
G6430) and memory controller are integrated onto the processor die * Package size: 14 mm × 14 × 1.0 mm


" SoFIA" (28 nm)

* SoFIA (''smart or feature phone with Intel architecture'') * All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel Burst Performance Technology (BPT), Intel VT-x, AES-NI (based on Silvermont's specs) * GPU ( ARM Mali) and memory controller are integrated onto the processor die * Package size: 34 × 40 mm * SoFIA 3G SoC with Silvermont CPU **Integrated HSPA+ A-GOLD 620: 2G/3G RF, CNV, PMU, Audio (Atom x3-C3130) Rockchip#Tablet processors with integrated modem * SoFIA 3G–R SoC with Silvermont CPU **Integrated HSPA+ A-GOLD 620: 2G/3G RF, CNV, PMU, Audio (Atom x3-C3230RK) * SoFIA LTE (W) with Airmont CPU (Announced, but never launched) **Integrated LTE Cat. 4 (XG726-based), SMARTi 4.5, LnP/ CG2000, PMIC (Atom x3-C3440 & C3445)


Tablet Tablet may refer to: Medicine * Tablet (pharmacy), a mixture of pharmacological substances pressed into a small cake or bar, colloquially called a "pill" Computing * Tablet computer, a mobile computer that is primarily operated by touching the s ...
processors/SoCs


Bonnell microarchitecture


" Lincroft" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Hyper-Threading. All except Z605 support Intel Burst Performance Technology (BPT). * GMA 600 GPU and DDR2 single-channel memory controller are integrated onto the processor die * Transistors: 140 million * Die size: 7.34 mm × 8.89 mm = 65.2526 mm² * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings: C0


" Cloverview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX bit implementation), Hyper-Threading, Intel Burst Performance Technology (BPT). * GPU and memory controller are integrated onto the processor die * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings:B1, C0 No official TDP available. For power data see page 129-130.


Silvermont microarchitecture


" Bay Trail-T" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel Burst Performance Technology (BPT), Intel VT-x, AES-NI, TXT/TXE * Package size: 17 mm × 17 × 1.0 mm Type 4 SoC:https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z36xxx-z37xxx-datasheet-vol-1.pdf * DDR3L single-channel or LPDDR3 dual-channel memory controller supporting up to 4 GB; ECC supported in single-channel mode * Display controller with 2 MIPI DSI ports and 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a) * Integrated Intel HD Graphics (Gen7) GPU * One USB 3.0 controller supporting one USB 3.0 port (can be multiplexed to support four USB 2.0 ports) * One USB 2.0 controller supporting four ports * Integrated LPE audio controller * Integrated image signal processor supporting two MIPI CSI ports, 24 MP sensors, and stereoscopic video * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM Type 3 SoC: * DDR3L/L-RS single-channel memory controller supporting up to 2 GB * Display controller with 1 MIPI DSI port and 2 DDI ports (HDMI 1.4) * Integrated Intel HD Graphics (Gen7) GPU * One USB controller supporting two USB 2.0 ports * Integrated LPE audio controller * Integrated image signal processor supporting two MIPI CSI ports and 8 MP sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Airmont microarchitecture


" Cherry Trail-T" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x2 (VT-x with EPT, FlexMigration, FlexPriority and VPID), AES-NI., TXT/TXE * Package size: 17 mm × 17 × 1.0 mm Type 4 SoC: * LPDDR3 dual-channel memory controller supporting up to 8 GB * PCI Express 2.0 controller with 2 lanes * Display controller with 2 MIPI DSI ports and 3 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen8) GPU * One USB xHCI controller supporting three USB 3.0 ports, two SSCI ports, and two HSIC ports * One USB xDCI controller supporting one USB 3.0 port * Integrated LPE audio controller * Integrated image signal processor supporting three MIPI CSI ports and 13 MP ZLS sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM Type 3 SoC: * DDR3L/L-RS single-channel memory controller supporting up to 2 GB * PCI Express 2.0 controller with 1 lane * Display controller with 2 MIPI DSI ports and 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen8) GPU * One USB controller supporting three USB 2.0 ports and two HSIC ports * Integrated LPE audio controller * Integrated image signal processor supporting three MIPI CSI ports and 8 MP sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Embedded processors/ SoCs


Bonnell microarchitecture


"

Tunnel Creek Tunnel Creek is a creek located within the grounds of Tunnel Creek National Park in the Kimberley region of Western Australia. Along with Geikie Gorge and Windjana Gorge, Tunnel Creek is part of an ancient barrier reef that developed during ...
" (45 nm)

* CPU core supports IA-32 architecture, MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), hyper-threading, Intel VT-x. * Package size: 22 mm × 22 mm * Steppings: B0 * Temperature range: for (E620, E640, E660, E680): 0 °C to +70 °C, for (E620T, E640T, E660T, E680T): -40 °C to +85 °C. * DDR2 single-channel memory controller supporting up to 2 GB * PCI Express 1.0a controller with 4 lanes * Display controller with LVDS and serial DVO ports * Integrated GMA600 (PowerVR) GPU * Integrated HD audio controller * Serial I/O supporting SPI


"

Stellarton Stellarton is a town located in the Canadian province of Nova Scotia. It is adjacent and to the south of the larger town of New Glasgow. In pioneer times the area was called Coal Mines Station, and from 1833 until 1889, it was known as Albion Min ...
" (45 nm)

* "
Tunnel Creek Tunnel Creek is a creek located within the grounds of Tunnel Creek National Park in the Kimberley region of Western Australia. Along with Geikie Gorge and Windjana Gorge, Tunnel Creek is part of an ancient barrier reef that developed during ...
" CPU with an Altera Field Programmable Gate Array (FPGA) * CPU core supports IA-32 architecture, MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Hyper-Threading, Intel VT-x * Package size: 37.5 mm × 37.5 mm * Steppings: B0 * TDP without FPGA. Total package TDP depends on functions included in FPGA. Max. TDP 7 W. * Temperature range: for (E625C, E645C, E665C): 0 °C to +70 °C, for (E625CT, E645CT, E665CT): -40 °C to +85 °C. * DDR2 single-channel memory controller supporting up to 2 GB * PCI Express 1.0a controller with 4 lanes * Display controller with LVDS and serial DVO ports * Integrated GMA600 (PowerVR) GPU * Integrated HD audio controller * Serial I/O supporting SPI


Silvermont microarchitecture


" Bay Trail-I" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI, TXT/TXE * Package size: 25 mm × 27 mm * DDR3L dual-channel memory controller supporting up to 4 GB; ECC supported in single-channel mode * Display controller with 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a) * Integrated Intel HD Graphics (Gen7) GPU * PCI Express 2.0 controller with four lanes and four root ports * Two SATA-300 ports * One USB 3.0 controller supporting one USB 3.0 port (can be multiplexed to support four USB 2.0 ports) * One USB 2.0 controller supporting four ports * Integrated LPE and HD audio controllers * Integrated image signal processor supporting three MIPI CSI ports, 24 MP sensors, and stereoscopic video * Integrated memory card reader supporting SDIO 3.0, eMMC 4.5, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Airmont microarchitecture


" Braswell" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI. * GPU and memory controller are integrated onto the processor die * GPU is based on Broadwell Intel HD Graphics, with 12 execution units, and supports DirectX 11.2, OpenGL 4.3, OpenGL ES 3.0 and OpenCL 1.2 (on Windows). * Package size: 25 mm × 27 mm


Goldmont microarchitecture


"

Apollo Lake Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core. The ''Apollo Lake'' platform with 14 nm Goldmont core was unv ...
" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, AES-NI, TXT/TXE * Package size: 24 mm × 31 mm * DDR3L/LPDDR3/LPDDR4 dual-channel memory controller supporting up to 8 GB; support for DDR3L with ECC * Display controller with 1 MIPI DSI port and 2 DDI ports (eDP 1.3, DP 1.1a, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen9) GPU * PCI Express 2.0 controller supporting 6 lanes (3 dedicated and 3 multiplexed with USB 3.0); 4 lanes available externally * Two USB 3.0 ports (1 dual role, 1 dedicated, 3 multiplexed with PCI Express 2.0 and 1 multiplexed with one SATA-300 port) * Two USB 2.0 ports * Two SATA-600 ports (one multiplexed with USB 3.0) * Integrated HD audio controller * Integrated image signal processor supporting four MIPI CSI ports and 13 MP sensors * Integrated memory card reader supporting SDIO 3.01 and eMMC 5.0 * Serial I/O supporting SPI, HSUART (serial port) and I2C


Tremont microarchitecture


" Elkhart Lake" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, AES-NI. * GPU is based on Gen11 Intel HD Graphics, with up to 32 execution units, and supports up to 3 displays (4K @ 60 Hz) through HDMI, DP, eDP, or DSI. * SoC peripherals include 4 × USB 2.0/3.0/3.1, 2 × SATA, 3 × 2.5GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, UART, and up to 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
3.0 in x4, x2, and x1 configurations. * Package size: 35 mm × 24 mm


Server SoCs

All Atom server processors include ECC support.


Bonnell microarchitecture


" Centerton" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Hyper-threading, Intel 64, Intel VT-x, ECC memory.


" Briarwood" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Hyper-threading, Intel 64, Intel VT-x, ECC memory.


Silvermont microarchitecture


" Avoton" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel Turbo Boost, Intel 64 (according to Datasheet), XD bit (an NX bit implementation), Intel VT-x, AES-NI, ECC memory. * Dual-core SoC peripherals include 4 × USB 2.0, 2 × SATA, 2 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 × UART, and 4 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
2.0, in x4, x2, and x1 configurations. * Quad-core SoC peripherals include 4 × USB 2.0, 2 (C2530) or 6 (C2550) × SATA, 2 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 × UART, and 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
2.0, in x8, x4, x2, and x1 configurations. * C2730 SoC peripherals include 4 × USB 2.0, 2 × SATA, 2 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 × UART, and 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
2.0, in x8, x4, x2, and x1 configurations. * C2750 SoC peripherals include 4 × USB 2.0, 6 × SATA, 4 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 × UART, and 16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
2.0, in x16, x8, x4, x2, and x1 configurations. * Package size: 34 mm × 28 mm * Die size: 107 mm²


" Rangeley" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel Turbo Boost, Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI, ECC memory. * All models except C2x38 support ''Intel QuickAssist Technology'' (cryptography accelerator) * SoC peripherals include 4 × USB 2.0, 4-6 × SATA (1 for C2308, 2 for C2316, C2508, C2516), 4 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
(2 for C2316), 2 × UART, and 8-16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
2.0 (4 lanes for C2308), in x16, x8, x4, x2, and x1 configurations. * Package size: 34 mm × 28 mm


Goldmont microarchitecture


" Denverton" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel Turbo Boost (dual-core, C3xx0, C3xx5 only), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, AES-NI, ECC memory. * SoC peripherals include 8–16 × USB 3.0, 6–16 × SATA, 4 × Integrated 1GbE, 2.5GbE, and
10GbE 10 Gigabit Ethernet (10GE, 10GbE, or 10 GigE) is a group of computer networking technologies for transmitting Ethernet frames at a rate of 10 gigabits per second. It was first defined by the IEEE 802.3ae-2002 standard. Unlike previous Eth ...
(C3538 and up)
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, and up to 20 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
3.0, in x8, x4, and x2 configurations. * Package size: 34 mm × 28 mm


Tremont microarchitecture


"

Snow Ridge Snow comprises individual ice crystals that grow while suspended in the atmosphere—usually within clouds—and then fall, accumulating on the ground where they undergo further changes. It consists of frozen crystalline water throughout ...
" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI, ECC memory. * Same frequency for all models: 2.2 GHz. L2 cache: 4.5 MB per module; each module comprises four CPU cores. * SoC peripherals include 4 × USB 3.0, 4 × USB 2.0, 16 × SATA, Integrated Intel Ethernet 800 series 100Gbps
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 3 × UART, and up to 32 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
(16 × 2.0, 16 × 3.0), in x16, x8, and x4 configurations. * Intel Dynamic Load Balancer (Intel DLB) & Intel QuickAssist Technology (Intel QAT) * P####B models are designed for base transceiver stations, especially that for 5G networks. All other models are designed for communications (extended temperature range). * Package size: 47.5 mm × 47.5 mm


" Parker Ridge" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI, ECC memory. * SoC peripherals include 4 × USB 3.0, 4 × USB 2.0, 16 × SATA, Integrated Intel Ethernet 800 series 100Gbps
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
(except 51xx model numbers), 3 × UART, and up to 32 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
(16 × 2.0, 16 × 3.0), in x16, x8, and x4 configurations. * Intel Dynamic Load Balancer (Intel DLB) & Intel QuickAssist Technology (Intel QAT) * Model numbers ending in 0 are extended temperature range; model numbers ending in 5 are commercial temperature range. * Package size: 47.5 mm × 47.5 mm


CE SoCs


Single-core CE SoCs


" Sodaville" (45 nm)

* Package size: 27 mm × 27 mm * GPU (based on the PowerVR SGX535 from Imagination Technologies)


" Groveland" (45 nm)

CE4200 * Package size: ?? mm × ?? mm * 2 × 32-bit memory channels, up to DDR2-800 * GPU (based on the PowerVR SGX535 from Imagination Technologies)


Dual-Core CE SoCs


" Berryville" (32 nm)

* Package size: ?? mm × ?? mm * GPU for 3D (based on the PowerVR SGX545 from Imagination Technologies) * GPU for 2D
GC300
from Vivante)


See also

* Atom (system on chip) * Comparison of Intel processors * List of Intel Celeron microprocessors * Intel GMA *
Stealey Stealey is the codename for a low-power x86 architecture microprocessor based on a ''Dothan'' core derived from the Intel Pentium M, built on a 90 nm process with 512 KB L2 cache and 400 MT/s front side bus (FSB). It was branded as Intel A100 and ...
(A100/A110) * Geode (processor) * VIA Nano * Intel Quark *
Intel Edison The Intel Edison is a computer-on-module that was offered by Intel as a development system for wearable devices and Internet of Things devices. The system was initially announced to be the same size and shape as an SD card and containing a dua ...


References


External links


Intel Atom Processor - Overview

SSPEC/QDF Reference
(Intel)
Intel Corporation - Processor Price List

Intel Atom and VIA Nano performance compared




{{DEFAULTSORT:Intel Atom Microprocessors *Atom Lists of microprocessors