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The Intel Atom is
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
's line of low-power, low-cost and low-performance
x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...
and
x86-64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
s. Atom, with codenames of '' Silverthorne'' and '' Diamondville'', was first announced on March 2, 2008. For Nettop and Netbook Atom Microprocessors after ''Diamondville'', the memory and graphics controller are moved from the northbridge to the CPU. This explains the drastically increased transistor count for post-''Diamondville'' Atom microprocessors.


Nettop processors (small desktop)


Bonnell microarchitecture


" Diamondville" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading * Transistors: 47 million * Die size: 25.96 mm² (3.27 × 7.94) * Package size: 22 mm × 22 mm


"

Pineview Pineview (also spelled Pine View) is a neighbourhood in Beacon Hill-Cyrville Ward in the east end of Ottawa, Ontario, Canada. Prior to amalgamation in 2001, the neighbourhood was part of the City of Gloucester. As of the Canada 2021 Census, the ...
" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading * Integrated GMA 3150 GPU and DDR3/DDR2 single-channel memory controller * Transistors: 123 million (single-core), 176 million (dual-core) * Die size: 66 mm² (9.56 × 6.89) (single-core), 87 mm² (9.56 × 9.06) (dual core) * Package size: 22 mm × 22 mm


" Cedarview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading (D2550, D2560, D2700, D2701 only) * Integrated PowerVR SGX545-based Intel
GMA 3600 The Intel Graphics Media Accelerator (GMA) is a series of integrated graphics processors introduced in 2004 by Intel, replacing the earlier Intel Extreme Graphics series and being succeeded by the Intel HD and Iris Graphics series. This series t ...
/ GMA 3650 GPU and DDR3 single-channel memory controllerhttps://www.intel.ca/content/dam/doc/datasheet/atom-d2000-n2000-vol-1-datasheet.pdf * Package size: 22 mm × 22 mm


Netbook Netbook was a commonly used term that identified a product class of small and inexpensive laptops which were sold from 2007 to around 2013. These machines were designed primarily as cost-effective tools for consumers to access the Inte ...
processors (sub-notebook)


Bonnell microarchitecture


" Diamondville" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading * Transistors: 47 million * Die size: 26 mm² * Package size: 22 mm × 22 mm


" Pineview" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading * Integrated GMA 3150 GPU and DDR3/DDR2 single-channel memory controller supporting up to 2 GB * Transistors: 123 million (single-core), 176 million (dual-core) * Die size: 66 mm² (9.56 × 6.89) (single-core), 87 mm² (9.56 × 9.06) (dual core) * Package size: 22 mm × 22 mm


" Cedarview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Intel 64, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading * Integrated PowerVR SGX545-based Intel
GMA 3600 The Intel Graphics Media Accelerator (GMA) is a series of integrated graphics processors introduced in 2004 by Intel, replacing the earlier Intel Extreme Graphics series and being succeeded by the Intel HD and Iris Graphics series. This series t ...
/ GMA 3650 GPU and DDR3 single-channel memory controller * Package size: 22 × 22 mm


MID processors/SoCs (

UMPC An ultra-mobile PC, or ultra-mobile personal computer (UMPC), is a miniature version of a pen computer, a class of laptop whose specifications were launched by Microsoft and Intel in spring 2006. Sony had already made a first attempt in this ...
/
Smartphone A smartphone is a portable computer device that combines mobile telephone and computing functions into one unit. They are distinguished from feature phones by their stronger hardware capabilities and extensive mobile operating systems, whic ...
/ IoT)


Bonnell microarchitecture


" Silverthorne" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading * Models Z520, Z520PT, Z530, Z530P, Z540, Z550 and Z560 support
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
* Model Z515 supports ''Intel Burst Performance Technology'' * Uses the
Poulsbo Poulsbo ( ) is a city on Liberty Bay in Kitsap County, Washington, United States. It is the smallest of the four cities in Kitsap County. The population was 9,200 at the 2010 census and an estimated 10,927 in 2018. The area was historically ...
chipset. * Transistors: 47 million * Die size: 26 mm² * Package size: 13 mm × 14 mm / 22 mm × 22 mm (processors ending with the ''P'' or ''PT'' sSpec number)


"

Lincroft Lincroft is an unincorporated community and census-designated place (CDP) within Middletown Township, in Monmouth County, New Jersey, United States.
" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading. All except Z605 support Intel Burst Performance Technology (BPT). * GMA 600 GPU and DDR2 single-channel memory controller are integrated into the processor.https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z6xx-datasheet.pdf * Transistors: 140 million * Die size: 7.34 mm × 8.89 mm = 65.2526 mm² * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings: C0


" Penwell" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Intel Burst Performance Technology (BPT), Hyper-Threading. * Integrated PowerVR SGX540 GPU and DDR3 single-channel memory controller * Package size: 12 mm × 12 × 1.0 mm


Silvermont microarchitecture


" Merrifield" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
, Intel Burst Performance Technology (BPT). * Z3480 also supports
Intel Wireless Display Wireless Display (WiDi) is technology developed by Intel that enables users to stream music, movies, photos, videos and apps without wires from a compatible computer to a compatible HDTV or through the use of an adapter with other HDTVs or mon ...
. * Integrated PowerVR G6400 GPU, memory controller supporting two 32-bit LPDDR3 channels up to 4 GB, USB 3.0 controller, eMMC 4.5 * Paired with Intel XMM 7160 LTE modem supporting 4G/3G/2G * Package size: 12 mm × 12 × 1.0 mm


" Moorefield" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
, Intel Burst Performance Technology (BPT),
Intel Wireless Display Wireless Display (WiDi) is technology developed by Intel that enables users to stream music, movies, photos, videos and apps without wires from a compatible computer to a compatible HDTV or through the use of an adapter with other HDTVs or mon ...
. * GPU (
PowerVR PowerVR is a division of Imagination Technologies (formerly VideoLogic) that develops hardware and software for 2D and 3D rendering, and for video encoding, decoding, associated image processing and DirectX, OpenGL ES, OpenVG, and OpenCL accele ...
G6430) and memory controller are integrated onto the processor die * Package size: 14 mm × 14 × 1.0 mm


"

SoFIA Sofia ( ; bg, София, Sofiya, ) is the Capital city, capital and List of cities and towns in Bulgaria, largest city of Bulgaria. It is situated in the Sofia Valley at the foot of the Vitosha mountain in the western parts of the country. ...
" (28 nm)

* SoFIA (''smart or feature phone with Intel architecture'') * All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Intel Burst Performance Technology (BPT),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
(based on Silvermont's specs) * GPU ( ARM Mali) and memory controller are integrated onto the processor die * Package size: 34 × 40 mm * SoFIA 3G SoC with Silvermont CPU **Integrated HSPA+ A-GOLD 620: 2G/3G RF, CNV, PMU, Audio (Atom x3-C3130) Rockchip#Tablet processors with integrated modem * SoFIA 3G–R SoC with Silvermont CPU **Integrated HSPA+ A-GOLD 620: 2G/3G RF, CNV, PMU, Audio (Atom x3-C3230RK) * SoFIA LTE (W) with Airmont CPU (Announced, but never launched) **Integrated LTE Cat. 4 (XG726-based), SMARTi 4.5, LnP/ CG2000, PMIC (Atom x3-C3440 & C3445)


Tablet processors/SoCs


Bonnell microarchitecture


"

Lincroft Lincroft is an unincorporated community and census-designated place (CDP) within Middletown Township, in Monmouth County, New Jersey, United States.
" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading. All except Z605 support Intel Burst Performance Technology (BPT). * GMA 600 GPU and DDR2 single-channel memory controller are integrated onto the processor die * Transistors: 140 million * Die size: 7.34 mm × 8.89 mm = 65.2526 mm² * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings: C0


" Cloverview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Hyper-Threading, Intel Burst Performance Technology (BPT). * GPU and memory controller are integrated onto the processor die * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings:B1, C0 No official TDP available. For power data see page 129-130.


Silvermont microarchitecture


" Bay Trail-T" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation), Intel Burst Performance Technology (BPT),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
, TXT/TXE * Package size: 17 mm × 17 × 1.0 mm Type 4 SoC:https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z36xxx-z37xxx-datasheet-vol-1.pdf * DDR3L single-channel or LPDDR3 dual-channel memory controller supporting up to 4 GB; ECC supported in single-channel mode * Display controller with 2 MIPI DSI ports and 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a) * Integrated Intel HD Graphics (Gen7) GPU * One USB 3.0 controller supporting one USB 3.0 port (can be multiplexed to support four USB 2.0 ports) * One USB 2.0 controller supporting four ports * Integrated LPE audio controller * Integrated image signal processor supporting two MIPI CSI ports, 24 MP sensors, and stereoscopic video * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM Type 3 SoC: * DDR3L/L-RS single-channel memory controller supporting up to 2 GB * Display controller with 1 MIPI DSI port and 2 DDI ports (HDMI 1.4) * Integrated Intel HD Graphics (Gen7) GPU * One USB controller supporting two USB 2.0 ports * Integrated LPE audio controller * Integrated image signal processor supporting two MIPI CSI ports and 8 MP sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Airmont microarchitecture


" Cherry Trail-T" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
2 (VT-x with EPT, FlexMigration, FlexPriority and VPID),
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
., TXT/TXE * Package size: 17 mm × 17 × 1.0 mm Type 4 SoC: * LPDDR3 dual-channel memory controller supporting up to 8 GB * PCI Express 2.0 controller with 2 lanes * Display controller with 2 MIPI DSI ports and 3 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen8) GPU * One USB xHCI controller supporting three USB 3.0 ports, two SSCI ports, and two HSIC ports * One USB xDCI controller supporting one USB 3.0 port * Integrated LPE audio controller * Integrated image signal processor supporting three MIPI CSI ports and 13 MP ZLS sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM Type 3 SoC: * DDR3L/L-RS single-channel memory controller supporting up to 2 GB * PCI Express 2.0 controller with 1 lane * Display controller with 2 MIPI DSI ports and 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen8) GPU * One USB controller supporting three USB 2.0 ports and two HSIC ports * Integrated LPE audio controller * Integrated image signal processor supporting three MIPI CSI ports and 8 MP sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Embedded Embedded or embedding (alternatively imbedded or imbedding) may refer to: Science * Embedding, in mathematics, one instance of some mathematical object contained within another instance ** Graph embedding * Embedded generation, a distributed ge ...
processors/ SoCs


Bonnell microarchitecture


"

Tunnel Creek Tunnel Creek is a creek located within the grounds of Tunnel Creek National Park in the Kimberley region of Western Australia. Along with Geikie Gorge and Windjana Gorge, Tunnel Creek is part of an ancient barrier reef that developed during ...
" (45 nm)

* CPU core supports
IA-32 IA-32 (short for "Intel Architecture, 32-bit", commonly called i386) is the 32-bit version of the x86 instruction set architecture, designed by Intel and first implemented in the 80386 microprocessor in 1985. IA-32 is the first incarnation of ...
architecture, MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST),
hyper-threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multi ...
,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
. * Package size: 22 mm × 22 mm * Steppings: B0 * Temperature range: for (E620, E640, E660, E680): 0 °C to +70 °C, for (E620T, E640T, E660T, E680T): -40 °C to +85 °C. * DDR2 single-channel memory controller supporting up to 2 GB * PCI Express 1.0a controller with 4 lanes * Display controller with LVDS and serial DVO ports * Integrated GMA600 (PowerVR) GPU * Integrated HD audio controller * Serial I/O supporting SPI


"

Stellarton Stellarton is a town located in the Canadian province of Nova Scotia. It is adjacent and to the south of the larger town of New Glasgow. In pioneer times the area was called Coal Mines Station, and from 1833 until 1889, it was known as Albio ...
" (45 nm)

* "
Tunnel Creek Tunnel Creek is a creek located within the grounds of Tunnel Creek National Park in the Kimberley region of Western Australia. Along with Geikie Gorge and Windjana Gorge, Tunnel Creek is part of an ancient barrier reef that developed during ...
" CPU with an Altera Field Programmable Gate Array (FPGA) * CPU core supports
IA-32 IA-32 (short for "Intel Architecture, 32-bit", commonly called i386) is the 32-bit version of the x86 instruction set architecture, designed by Intel and first implemented in the 80386 microprocessor in 1985. IA-32 is the first incarnation of ...
architecture, MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Hyper-Threading,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
* Package size: 37.5 mm × 37.5 mm * Steppings: B0 * TDP without FPGA. Total package TDP depends on functions included in FPGA. Max. TDP 7 W. * Temperature range: for (E625C, E645C, E665C): 0 °C to +70 °C, for (E625CT, E645CT, E665CT): -40 °C to +85 °C. * DDR2 single-channel memory controller supporting up to 2 GB * PCI Express 1.0a controller with 4 lanes * Display controller with LVDS and serial DVO ports * Integrated GMA600 (PowerVR) GPU * Integrated HD audio controller * Serial I/O supporting SPI


Silvermont microarchitecture


" Bay Trail-I" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
, TXT/TXE * Package size: 25 mm × 27 mm * DDR3L dual-channel memory controller supporting up to 4 GB; ECC supported in single-channel mode * Display controller with 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a) * Integrated Intel HD Graphics (Gen7) GPU * PCI Express 2.0 controller with four lanes and four root ports * Two SATA-300 ports * One USB 3.0 controller supporting one USB 3.0 port (can be multiplexed to support four USB 2.0 ports) * One USB 2.0 controller supporting four ports * Integrated LPE and HD audio controllers * Integrated image signal processor supporting three MIPI CSI ports, 24 MP sensors, and stereoscopic video * Integrated memory card reader supporting SDIO 3.0, eMMC 4.5, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Airmont microarchitecture


" Braswell" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
. * GPU and memory controller are integrated onto the processor die * GPU is based on Broadwell
Intel HD Graphics Intel Graphics Technology (GT) is the collective name for a series of integrated graphics processors (IGPs) produced by Intel that are manufactured on the same package or die as the central processing unit (CPU). It was first introduced in 201 ...
, with 12 execution units, and supports DirectX 11.2, OpenGL 4.3, OpenGL ES 3.0 and OpenCL 1.2 (on Windows). * Package size: 25 mm × 27 mm


Goldmont microarchitecture


"

Apollo Lake Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core. The ''Apollo Lake'' platform with 14 nm Goldmont core was unv ...
" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
, TXT/TXE * Package size: 24 mm × 31 mm * DDR3L/LPDDR3/LPDDR4 dual-channel memory controller supporting up to 8 GB; support for DDR3L with ECC * Display controller with 1 MIPI DSI port and 2 DDI ports (eDP 1.3, DP 1.1a, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen9) GPU * PCI Express 2.0 controller supporting 6 lanes (3 dedicated and 3 multiplexed with USB 3.0); 4 lanes available externally * Two USB 3.0 ports (1 dual role, 1 dedicated, 3 multiplexed with PCI Express 2.0 and 1 multiplexed with one SATA-300 port) * Two USB 2.0 ports * Two SATA-600 ports (one multiplexed with USB 3.0) * Integrated HD audio controller * Integrated image signal processor supporting four MIPI CSI ports and 13 MP sensors * Integrated memory card reader supporting SDIO 3.01 and eMMC 5.0 * Serial I/O supporting SPI, HSUART (serial port) and I2C


Tremont microarchitecture


" Elkhart Lake" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
. * GPU is based on Gen11
Intel HD Graphics Intel Graphics Technology (GT) is the collective name for a series of integrated graphics processors (IGPs) produced by Intel that are manufactured on the same package or die as the central processing unit (CPU). It was first introduced in 201 ...
, with up to 32 execution units, and supports up to 3 displays (4K @ 60 Hz) through
HDMI High-Definition Multimedia Interface (HDMI) is a proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controll ...
, DP, eDP, or DSI. * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0/3.0/3.1, 2 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, 3 × 2.5GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
,
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and up to 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
3.0 in x4, x2, and x1 configurations. * Package size: 35 mm × 24 mm


Server Server may refer to: Computing *Server (computing), a computer program or a device that provides functionality for other programs or devices, called clients Role * Waiting staff, those who work at a restaurant or a bar attending customers and su ...
SoCs

All Atom server processors include ECC support.


Bonnell microarchitecture


" Centerton" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
Hyper-threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multi ...
, Intel 64,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
.


" Briarwood" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
Hyper-threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multi ...
, Intel 64,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
.


Silvermont microarchitecture


" Avoton" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST),
Intel Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units (CPUs) dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher resulting ...
, Intel 64 (according to Datasheet), XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
. * Dual-core SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0, 2 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, 2 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and 4 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
2.0, in x4, x2, and x1 configurations. * Quad-core SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0, 2 (C2530) or 6 (C2550) ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, 2 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
2.0, in x8, x4, x2, and x1 configurations. * C2730 SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0, 2 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, 2 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
2.0, in x8, x4, x2, and x1 configurations. * C2750 SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0, 6 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, 4 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and 16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
2.0, in x16, x8, x4, x2, and x1 configurations. * Package size: 34 mm × 28 mm * Die size: 107 mm²


" Rangeley" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST),
Intel Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units (CPUs) dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher resulting ...
, Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
. * All models except C2x38 support ''Intel QuickAssist Technology'' (cryptography accelerator) * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0, 4-6 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
(1 for C2308, 2 for C2316, C2508, C2516), 4 × Integrated GbE
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
(2 for C2316), 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and 8-16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
2.0 (4 lanes for C2308), in x16, x8, x4, x2, and x1 configurations. * Package size: 34 mm × 28 mm


Goldmont microarchitecture


" Denverton" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST),
Intel Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units (CPUs) dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher resulting ...
(dual-core, C3xx0, C3xx5 only), Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
. * SoC peripherals include 8–16 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
3.0, 6–16 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, 4 × Integrated 1GbE, 2.5GbE, and
10GbE 10 Gigabit Ethernet (10GE, 10GbE, or 10 GigE) is a group of computer networking technologies for transmitting Ethernet frames at a rate of 10  gigabits per second. It was first defined by the IEEE 802.3ae-2002 standard. Unlike previous Et ...
(C3538 and up)
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, and up to 20 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
3.0, in x8, x4, and x2 configurations. * Package size: 34 mm × 28 mm


Tremont microarchitecture


" Snow Ridge" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
. * Same frequency for all models: 2.2 GHz. L2 cache: 4.5 MB per module; each module comprises four CPU cores. * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
3.0, 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0, 16 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, Integrated Intel Ethernet 800 series 100Gbps
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
, 3 ×
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and up to 32 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
(16 × 2.0, 16 × 3.0), in x16, x8, and x4 configurations. * Intel Dynamic Load Balancer (Intel DLB) & Intel QuickAssist Technology (Intel QAT) * P####B models are designed for
base transceiver station A base transceiver station (BTS) is a piece of equipment that facilitates wireless communication between user equipment (UE) and a network. UEs are devices like mobile phones (handsets), WLL phones, computers with wireless Internet connectivity, ...
s, especially that for 5G networks. All other models are designed for communications (extended temperature range). * Package size: 47.5 mm × 47.5 mm


"

Parker Ridge Parker Ridge is a mountain ridge located in the upper North Saskatchewan River valley in Banff National Park, in the Canadian Rockies of Alberta, Canada. Its nearest higher peak is Mount Athabasca, to the west. Parker Ridge is situated along th ...
" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Intel 64, XD bit (an
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
implementation),
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
. * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
3.0, 4 ×
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broa ...
2.0, 16 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host adapter, host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) ...
, Integrated Intel Ethernet 800 series 100Gbps
LAN Lan or LAN may also refer to: Science and technology * Local asymptotic normality, a fundamental property of regular models in statistics * Longitude of the ascending node, one of the orbital elements used to specify the orbit of an object in sp ...
(except 51xx model numbers), 3 ×
UART A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least signific ...
, and up to 32 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...
(16 × 2.0, 16 × 3.0), in x16, x8, and x4 configurations. * Intel Dynamic Load Balancer (Intel DLB) & Intel QuickAssist Technology (Intel QAT) * Model numbers ending in 0 are extended temperature range; model numbers ending in 5 are commercial temperature range. * Package size: 47.5 mm × 47.5 mm


CE SoCs


Single-core CE SoCs


" Sodaville" (45 nm)

* Package size: 27 mm × 27 mm * GPU (based on the PowerVR SGX535 from Imagination Technologies)


" Groveland" (45 nm)

CE4200 * Package size: ?? mm × ?? mm * 2 × 32-bit memory channels, up to DDR2-800 * GPU (based on the PowerVR SGX535 from Imagination Technologies)


Dual-Core CE SoCs


" Berryville" (32 nm)

* Package size: ?? mm × ?? mm * GPU for 3D (based on the PowerVR SGX545 from Imagination Technologies) * GPU for 2D
GC300
from
Vivante Vivante Corporation is a fabless semiconductor company headquartered in Sunnyvale, California, with an R&D center in Shanghai, China. The company was founded in 2004 as GiQuila and focused on the portable gaming market. The company's first prod ...
)


See also

*
Atom (system on chip) Atom is a system on a chip (SoC) platform designed for smartphones and tablet computers, launched by Intel in 2012. It is a continuation of the partnership announced by Intel and Google on September 13, 2011 to provide support for the Android op ...
* Comparison of Intel processors *
List of Intel Celeron microprocessors A ''list'' is any set of items in a row. List or lists may also refer to: People * List (surname) Organizations * List College, an undergraduate division of the Jewish Theological Seminary of America * SC Germania List, German rugby unio ...
*
Intel GMA The Intel Graphics Media Accelerator (GMA) is a series of integrated graphics processors introduced in 2004 by Intel, replacing the earlier Intel Extreme Graphics series and being succeeded by the Intel HD and Iris Graphics series. This serie ...
*
Stealey Stealey is the codename for a low-power x86 architecture microprocessor based on a ''Dothan'' core derived from the Intel Pentium M, built on a 90 nm process with 512 KB L2 cache and 400 MT/s front side bus (FSB). It was branded as Intel A100 and ...
(A100/A110) *
Geode (processor) Geode was a series of x86-compatible system-on-a-chip microprocessors and I/O companions produced by AMD, targeted at the embedded computing market. The series was originally launched by National Semiconductor as the Geode family in 1999. T ...
*
VIA Nano The VIA Nano (formerly code-named VIA Isaiah) is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development by its CPU division, Centaur Technology. This new Isaiah 64-bit architec ...
*
Intel Quark Intel Quark is a line of 32-bit x86 SoCs and microcontrollers by Intel, designed for small size and low power consumption, and targeted at new markets including wearable devices. The line was introduced at Intel Developer Forum in 2013, and d ...
*
Intel Edison The Intel Edison is a computer-on-module that was offered by Intel as a development system for wearable devices and Internet of Things devices. The system was initially announced to be the same size and shape as an SD card and containing a d ...


References


External links


Intel Atom Processor - Overview

SSPEC/QDF Reference
(Intel)
Intel Corporation - Processor Price List

Intel Atom and VIA Nano performance compared




{{DEFAULTSORT:Intel Atom Microprocessors *Atom Lists of microprocessors