Nehalem is the

codename A code name, codename, call sign, or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in ...

for

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...

45 nm Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame. Matsushita and Intel started mas ...

microarchitecture In electronics, computer science and computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as μarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular ...

released in November 2008. It was used in the first generation of the

Intel Core Intel Core is a line of multi-core (with the exception of Core Solo and Core 2 Solo) central processing units (CPUs) for midrange, embedded, workstation, high-end and enthusiast computer markets marketed by Intel Corporation. These processors ...

i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The term "Nehalem" comes from the

Nehalem River The Nehalem River is a river on the Pacific coast of northwest Oregon in the United States, approximately long. It drains part of the Northern Oregon Coast Range northwest of Portland, originating on the east side of the mountains and flowing in ...

. Nehalem is built on the

process, is able to run at higher clock speeds without sacrificing efficiency, and is more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem is an architecture that differs radically from

NetBurst The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium ...

, while retaining some of the latter's minor features. Nehalem later received a die-shrink to

32 nm The "32 nm" node is the step following the "45 nm" process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technolo ...

with Westmere, and was fully succeeded by "second-generation"

Sandy Bridge Sandy Bridge is the List of Intel codenames, codename for Intel's 32 nm process, 32 nm microarchitecture used in the second generation of the Intel Core, Intel Core processors (Intel Core i7, Core i7, Intel Core i5, i5, Intel Core i3, i3). The Sa ...

in January 2011.

Technology

* Cache line block on L2/L3 cache was reduced from 128 bytes in NetBurst & Merom/Penryn to 64 bytes per line in this generation (same size as Yonah and Pentium M). * Hyper-threading reintroduced. * Intel

Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units' (CPUs') dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher result ...

1.0. * 2–24 MiB

L3 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...

with

Smart Cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...

in some models. *

Instruction Fetch Unit The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetch ...

(IFU) containing second-level

branch predictor In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow ...

with two level

Branch Target Buffer In computer architecture, a branch target predictor is the part of a processor that predicts the target, i.e., the address of the instruction that is executed next, of a taken conditional branch or unconditional branch instruction before the ta ...

(BTB) and Return Stack Buffer (RSB). Nehalem also supports all predictor types previously used in Intel's processors like Indirect Predictor and Loop Detector. * sTLB (second level unified

translation lookaside buffer A translation lookaside buffer (TLB) is a memory CPU cache, cache that stores the recent translations of virtual memory address to a physical memory Memory_address, location. It is used to reduce the time taken to access a user memory location. It ...

) (i.e. both instructions and data) that contains 512 entries for small pages only, and is again 4 way associative. * 3 integer ALU, 2 vector ALU and 2 AGU per core. * Native (all processor cores on a single die) quad- , hex-, and octa-core processors *

Intel QuickPath Interconnect The Intel QuickPath Interconnect (QPI) is a scalable processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available b ...

in HEDT, server, and workstation models and

Direct Media Interface In computing, Direct Media Interface (DMI) is Intel's proprietary link between the northbridge (or CPU) and southbridge (e.g. Platform Controller Hub family) chipset on a computer motherboard. It was first used between the 9xx chipsets and t ...

on other models replacing the legacy

front side bus The front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the ...

. * 64 KB L1 cache per core (32 KB L1 data and 32 KB L1 instruction), and 256 KB L2 cache per core. * Integration of

PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...

and

DMI DMI may refer to: Organizations * Danish Meteorological Institute * Data Management Inc., a time-and-attendance software company * Dead Man Incorporated, a predominantly white prison-gang formed in Maryland * Development Media International, a ...

into the processor in mid-range models, replacing the northbridge. * Integrated

memory controller A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer's main memory. When a memory controller is integrated into anothe ...

supporting two or three memory channels of

DDR3 SDRAM Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-spe ...

or four FB-DIMM2 channels. * Second-generation Intel Virtualization Technology, which introduced

Extended Page Table Second Level Address Translation (SLAT), also known as nested paging, is a hardware-assisted virtualization technology which makes it possible to avoid the overhead associated with software-managed shadow page tables. AMD has supported SLAT throu ...

support, virtual processor identifiers (VPIDs), and

non-maskable interrupt In computing, a non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore. It typically occurs to signal attention for non-recoverable hardware errors. Some NMIs may be masked, but ...

-window exiting. * SSE4.2 and POPCNT instructions. *

Macro-op fusion In computer central processing units, micro-operations (also known as micro-ops or μops, historically also as micro-actions) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed m ...

now works in 64-bit mode. * 20 to 24 pipeline stages. :

Performance and power improvements

It has been reported that Nehalem has a focus on performance, thus the increased core size. Compared to Penryn, Nehalem has: * 10–25% better single-threaded performance / 20–100% better multithreaded performance at the same power level * 30% lower

power consumption Electric energy consumption is energy consumption in the form of electrical energy. About a fifth of global energy is consumed as electricity: for residential, industrial, commercial, transportation and other purposes. The global electricity con ...

for the same

performance A performance is an act or process of staging or presenting a play, concert, or other form of entertainment. It is also defined as the action or process of carrying out or accomplishing an action, task, or function. Performance has evolved glo ...

* On average, Nehalem provides a 15–20% clock-for-clock increase in performance per core. Overclocking is possible with Bloomfield processors and the X58 chipset. Lynnfield processors use a PCH removing the need for a northbridge. Nehalem processors incorporate SSE4.2

SIMD Single instruction, multiple data (SIMD) is a type of parallel computer, parallel processing in Flynn's taxonomy. SIMD describes computers with multiple processing elements that perform the same operation on multiple data points simultaneousl ...

instructions, adding seven new instructions to the SSE 4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate overhead on atomic operations such as the LOCK CMPXCHG

compare-and-swap In computer science, compare-and-swap (CAS) is an atomic instruction used in multithreading to achieve synchronization. It compares the contents of a memory location with a given (the previous) value and, only if they are the same, modifies the ...

instruction.

Variants

* Lynnfield processors feature 16

PCIe PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...

lanes, which can be used in 1x16 or 2x8 configuration. * ¹ 6500 series scalable up to 2 sockets, 7500 series scalable up to 4/8 sockets.

Server, workstation, and desktop processors

* Intel states the Gainestown processors have six memory channels. Gainestown processors have dual QPI links and have a separate set of memory registers for each link in effect, a multiplexed six-channel system.

Mobile processors

References

External links

Nehalem processor
at

.com {{Intel processor roadmap Intel x86 microprocessors Intel microarchitectures X86 microarchitectures Computer-related introductions in 2008