Emerald Rapids is the
codename
A code name, codename, call sign, or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in ...
for
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
's fifth generation
Xeon
Xeon (; ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded markets. It was introduced in June 1998. Xeon processors are based on the same archite ...
Scalable server processors based on the
Intel 7 node. Emerald Rapids CPUs are designed for data centers; the roughly contemporary
Raptor Lake
Raptor Lake is Intel's List of Intel codenames, codename for the 13th and 14th generations of Intel Core processors based on a Heterogeneous computing, hybrid architecture, utilizing Raptor Cove performance cores and Gracemont (microarchitecture ...
is intended for desktop and mobile usage. Nevine Nassif is a chief engineer for this generation.
Features
CPU
* Up to 64
Raptor Cove CPU cores per package
** Up to 32 cores per tile, reducing the max tiles to two
* 5 MB of L3 cache per core (up from 1.875 MB in Sapphire Rapids)
* Speed Select Technology that supports high and low priority cores
I/O
*
DDR5
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. The ...
memory support up to 8-channel DDR5-5600
* Up to 80
PCI Express 5.0 lanes
List of Emerald Rapids processors
Emerald Rapids-SP (Scalable Performance)
CPUs in ''italic'' are actually Sapphire Rapids processors, and they still have 1.875 MB of L3 cache per core
See also
* Intel's
process–architecture–optimization model
Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor
A microprocessor is a computer processor (computi ...
* Intel's
tick–tock model
Tick–tock was a production model adopted in 2007 by integrated circuit, chip manufacturer Intel. Under this model, every new process technology was first used to manufacture a die shrink of a proven microarchitecture (tick), followed by a new mic ...
*
List of Intel CPU microarchitectures
References
{{Intel processor roadmap
Intel products
Intel microprocessors