Elmore delay
is a simple approximation to the delay through an
RC network in an electronic system. It is often used in applications such as
logic synthesis,
delay calculation,
static timing analysis
Static timing analysis (STA) is a simulation method of computing the expected timing of a Synchronous circuit, synchronous digital circuit without requiring a simulation of the full circuit.
High-performance integrated circuits have tradition ...
,
placement and
routing
Routing is the process of selecting a path for traffic in a network or between or across multiple networks. Broadly, routing is performed in many types of networks, including circuit-switched networks, such as the public switched telephone netw ...
, since it is simple to compute (especially in
tree structured networks, which are the vast majority of signal nets within ICs) and is reasonably accurate. Even where it is not accurate, it is usually faithful, in the sense that reducing the Elmore delay will almost always reduce the true delay, so it is still useful in optimization.
Elmore delay can be thought of in several ways, all mathematically identical.
*For tree structured networks, find the delay through each segment as the R (
electrical resistance) times the downstream C (electrical
capacitance). Sum the delays from the
root to the
sink.
*Assume the output is a simple exponential, and find the exponential that has the same integral as the true response. This is also equivalent to ''moment matching'' with one moment, since the first moment is a pure exponential.
*Find a one pole approximation to the true frequency response. This is a first-order
Padé approximation.
There are many extensions to Elmore delay. It can be extended to upper and lower bounds,
to include
inductance
Inductance is the tendency of an electrical conductor to oppose a change in the electric current flowing through it. The flow of electric current creates a magnetic field around the conductor. The field strength depends on the magnitude of the ...
as well as R and C, to be more accurate (higher order approximations)
and so on. See
delay calculation for more details and references.
See also
*
Delay calculation
*
Static timing analysis
Static timing analysis (STA) is a simulation method of computing the expected timing of a Synchronous circuit, synchronous digital circuit without requiring a simulation of the full circuit.
High-performance integrated circuits have tradition ...
*
William Cronk Elmore
William Cronk Elmore (September 16, 1909 – January 23, 2003) was an American physicist, educator, and author who is best known for his work on and related to the Manhattan project during World War II and as a professor of physics at Swarthmore Co ...
References
{{reflist , refs=
[W.C. Elmore. {{doi-inline, 10.1063/1.1697872, The Transient Analysis of Damped Linear Networks with Particular Regard to Wideband Amplifiers, J. Applied Physics, vol. 19(1), 1948.]
[Gupta, R., Tutuianu, B., Pileggi, L.T., {{doi-inline, 10.1109/43.559334, The Elmore delay as a bound for RC trees with generalized input signals, IEEE Transactions on the Computer-Aided Design of Integrated Circuits and Systems, Volume: 16, Issue: 1, pp. 95-104.]
[Tutuianu, B., Dartu, F., and Pileggi, L]
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
Proceedings of the Design Automation Conference, Las Vegas, NV, 1996, pp. 611-616
Electronic engineering
Electronic design
Electronic design automation
Integrated circuits