In digital electronic design a clock domain crossing (CDC), or simply

clock A clock or a timepiece is a device used to measure and indicate time. The clock is one of the oldest human inventions, meeting the need to measure intervals of time shorter than the natural units such as the day, the lunar month and t ...

crossing, is the traversal of a signal in a synchronous

digital circuit In theoretical computer science, a circuit is a model of computation in which input values proceed through a sequence of gates, each of which computes a function. Circuits of this kind provide a generalization of Boolean circuits and a mathematica ...

from one

domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary. A synchronous system is composed of a single

electronic oscillator An electronic oscillator is an electronic circuit that produces a periodic, oscillating electronic signal, often a sine wave or a square wave or a triangle wave. Oscillators convert direct current (DC) from a power supply to an alternating cur ...

that generates a

clock signal In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits. A clock s ...

, and its clock domain—the memory elements directly clocked by that signal from that oscillator, and the combinational logic attached to the outputs of those memory elements. Because of speed-of-light delays, timing skew, etc., the size of a clock domain in such a synchronous system is inversely proportional to the frequency of the clock. In early computers, typically all the digital logic ran in a single clock domain. Because of

transmission line In electrical engineering, a transmission line is a specialized cable or other structure designed to conduct electromagnetic waves in a contained manner. The term applies when the conductors are long enough that the wave nature of the transmi ...

loss and distortion it is difficult to carry digital signals above 66 MHz on standard

PCB PCB may refer to: Science and technology * Polychlorinated biphenyl, an organic chlorine compound, now recognized as an environmental toxin and classified as a persistent organic pollutant * Printed circuit board, a board used in electronics * ...

traces (the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are single-chip CPUs with a

phase-locked loop A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a ...

(PLL) or other on-chip oscillator, keeping the fastest signals on-chip. At first, each CPU chip ran in its own single clock domain, and the rest of the digital logic of the computer ran in another slower clock domain. A few modern CPUs have such a high speed clock, that designers are forced to create several different clock domains on a single CPU chip. Different

domains have clocks which have a different

frequency Frequency is the number of occurrences of a repeating event per unit of time. It is also occasionally referred to as ''temporal frequency'' for clarity, and is distinct from '' angular frequency''. Frequency is measured in hertz (Hz) which is ...

, a different phase (due to either differing clock latency or a different clock source), or both. Either way the relationship between the clock edges in the two domains cannot be relied upon. Synchronizing a single bit signal to a clock domain with a higher frequency can be accomplished by registering the signal through a flip-flop that is clocked by the source domain, thus holding the signal long enough to be detected by the higher frequency clocked destination domain. CDC metastability issues can occur between asynchronous clock domains; this is in contrast to reset domain crossing metastability, which can occur between synchronous & asynchronous clock domains. To avoid issues with CDC metastability in the destination clock domain, a minimum of 2 stages of re-synchronization flip-flops are included in the destination domain. Synchronizing a single bit signal traversing into clock domain with a slower frequency is more cumbersome. This typically requires a register in each clock domain with a form of feedback from the destination domain to the source domain, indicating that the signal was detected. Other potential clock domain crossing design errors include glitches and data loss.SemiEngineering: Clock Domain Crossing (CDC)
/ref> In some cases, clock gating can result in two clock domains where the "slower" domain changes from one second to the next.

See also

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Further reading