Registers and memory map
The COP8 uses separate instruction and data spaces ( Harvard architecture). Instruction address space is 15-bit (32 KiB maximum), while data addresses are 8-bit (256 bytes maximum, extended via bank-switching). To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction. Invalid RAM above the stack reads as all-ones, which is an invalid address. The CPU has an 8-bit accumulator and 15-bitControl transfers
In addition to 3-byte and instructions which can address the entire address space, 2-byte versions of these instructions can jump within a 4K page. The instruction specifies the low 12 bits, and the high 3 bits of the PC are preserved. (These are intended primarily for models with up to 4K of ROM.) There are also jump indirect and load accumulator indirect instructions which use the accumulator contents as the low 8 bits of an address; the high 7 bits of the current PC are preserved. For short-distance branches, there are 63 1-byte instructions which perform PC-relative branches from PC−32 to PC+31. This is a 15-bit addition, and no page boundary requirements apply. Conditional branches ''per se'' do not exist, nor does the processor provide the traditional ZCVN status flags, although the program status word contains carry and half-carry flags for multi-byte arithmetic. Rather, there are a number of compare-and-skip instructions. For example, compares its two operands, and skips the following instruction if they are unequal. Any instruction may be skipped; it is not limited to branches. A feature unique to the COP8 architecture is the instruction. This compares the low 4 bits of the B (memory pointer) register with a 4-bit immediate constant, and can be used to loop until B has reaches the end of a small (up to 16 byte) buffer. An interesting extension of this mechanism is the return-and-skip instruction, which lets any subroutine call conditionally skip the following instruction. This provides a very compact way to return a boolean value from a subroutine.Instruction set
COP8 operands are listed in destination, source order. Most instructions have the accumulator A as one of the operands. The other operand is generally chosen from an 8-bit immediate value, an 8-bit RAM address, or , the RAM address selected by the B register. Some instructions also support RAM addressing by the X register (), and post-inc/decrement variants (, , , ). Indirect addressing via B is particularly fast, and can be done in the same cycle that the instruction is executed. On the other hand, absolute RAM addressing is not directly encoded in most cases. Rather, a special "direct addressing" prefix opcode, followed by a 1-byte address, may precede any instruction with a operand, and changes it to a memory direct operand. This adds two bytes and three cycles to the instruction. (Conditional-skip instructions skip the prefix and following instruction as a pair.) All "move" instructions are called (load) even if the destination is a memory address. Unusually, there are no instructions with the accumulator as a source; stores are done with the instruction which ''exchanges'' the accumulator with the memory operand, storing A and loading the previous memory contents. (This takes no additional time; is a one-cycle instruction.) There are instructions to fetch from tables in ROM. These combine the high 7 bits of the program counter (PCU) with the accumulator, fetch a byte from that address, and place it in the accumulator ( instruction) or the low 8 bits of the program counter PCL ( instruction). Because the next instruction executed must be in the same 256-byte page of ROM as the table itself, a 256-entry table is not possible.References
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