2 Nm Process

In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node. , TSMC is expected to begin production sometime after 2023; Intel also forecasts production by 2024.

The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the semiconductor chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a
higher degree of miniaturization), increased speed and reduced power consumption.

Background

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.

TSMC began research on 2 nm in 2019. TSMC expected to transition from FinFET to GAAFET transistor types when moving from 3 nm to 2 nm.

Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027 respectively. In December 2019, Intel announced plans for 1.4 nm production in 2029.

In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021. In September 2020 (SEMICON Taiwan 2020) it was reported that TSMC Chairman Mark Liu had stated the company would build a plant for the 2 nm node at Hsinchu in Taiwan, and that it could also install production at Taichung dependent on demand. According to the Taiwan Economic Daily (2020) expectations were for high yield risk production in late 2023. In July 2021, TSMC received governmental approval to build its 2 nm plant; according to Nikkei the company expects to install production equipment for 2 nm by 2023.

At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm, as well as designing and manufacturing custom processors, assigning up to 145 billion euro in funds.

In May 2021, IBM announced it had produced 2 nm class transistor using three silicon layer nanosheets with a gate length of 12 nm.12nm gate length is the dimension defined by the IRDS 2020 to be associated with the "1.5nm" process node

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In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their 2 nm process node called Intel 20A, with the "A" referring to angstrom, a unit equivalent to 0.1 nanometer. At the same time they introduced a new process node naming scheme that aligned their product names to similar designations from their main competitors. Intel's 20A node is projected to be their first to move from FinFET to Gate-All-Around transistors ( GAAFET); Intel's version is named 'RibbonFET'. Their 2021 roadmap scheduled the Intel 20A node for introduction in 2024.

Beyond 2 nm

Intel has planned 18A (equivalent to 1.8 nm) products for 2025.

Notes

References

Further reading

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{{sequence
, prev = 3 nm (FinFET/ GAAFET)
, list = MOSFET semiconductor device fabrication process
, next = unknown

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