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OpenPOWER
The OpenPOWER Foundation is a collaboration around Power ISA-based products initiated by IBM and announced as the "OpenPOWER Consortium" on August 6, 2013. IBM is opening up technology surrounding their Power Architecture offerings, such as processor specifications, firmware and software with a liberal license, and will be using a collaborative development model with their partners. The goal is to enable the server vendor ecosystem to build their own customized server, networking and storage hardware for future data centers and cloud computing. The governing body around the Power ISA instruction set is now the OpenPOWER Foundation: IBM allows its patents to be royalty-free for Compliant implementations. Processors based on IBM's IP can now be fabricated on any foundry and mixed with other hardware products of the integrator's choice. On August 20, 2019, IBM announced that the OpenPOWER Foundation would become part of the Linux Foundation. Openness IBM is using the word "o ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
POWER8
POWER8 is a family of superscalar multi-core microprocessors based on the Power ISA, announced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for such availability of IBM's highest-end processors. Systems based on POWER8 became available from IBM in June 2014. Systems and POWER8 processor designs made by other OpenPOWER members were available in early 2015. Design POWER8 is designed to be a massively multithreaded chip, with each of its cores capable of handling eight hardware threads simultaneously, for a total of 96 threads executed simultaneously on a 12-core chip. The processor makes use of very large amounts of on- and off-chip eDRAM caches, and on-chip memory controllers enable very high bandwidth to memory and system I/O. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the POWER7. POWER8 chips comes in 6- or 12-core variants ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Libre-SOC
Libre-SOC is a libre soft processor core originally written by Luke Leighton and other contributors, announced at the OpenPOWER Summit NA 2020. It adheres to the Power ISA 3.0 instruction set and can be run on FPGA boards, currently booting MicroPython and other bare-metal applications. The purpose of Libre-SOC is to be a system on a chip (SoC) with 3D and video capability built-in as part of the Power ISA, suitable for single-board computers, netbooks, IoT devices and other small form factors, while retaining a completely free and open design. History Libre-SOC began its life when Luke Leighton wanted there to be a completely free and libre system on a chip offering. He initially opted for a RISC-V base, but later switched to OpenPOWER when that seemed like a better fit for the project. It is the second processor written from scratch using the OpenPOWER ISA 3.0, and the first libre core that is completely independent of IBM. The project is mostly funded through NLnet ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Power ISA
Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several ''categories'' which are described in a certain ''Book''. Processors implement a set of these categories as required for their task. Different classes of processors are required to implement certain categories, for example a server-class processor includes the categories: ''Base'', ''Server'', ''Floating-Point'', ''64-Bit'', etc. All processors implement the Base category. Power ISA is a RISC load/store architecture. It has multiple sets of registers: * ''32'' × 32-bi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM A2
The IBM A2 is an open source massively multicore capable and multithreaded 64-bit Power ISA processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core version, consuming 20 W at 1.4 GHz. Design The A2 core is a processor core designed for customization and embedded use in system on chip-devices, and was developed following IBM's game console processor designs, the Xbox 360-processor and Cell processor for the PlayStation 3. A2I A2I is a 4-way simultaneous multithreaded core which implements the 64-bit Power ISA v.2.06 Book III-E embedded platform specification with support for the embedded hypervisor features. It was designed for implementations with many cores and focusing on high throughput and many simultaneous threads. A2I was written in VHDL. The core has 4×32 64-bit general purpose registers (GPR) w ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Power Architecture Platform Reference
Power Architecture Platform Reference (PAPR) is an initiative from Power.org to make a new open computing platform based on Power ISA processors. It follows two previous attempts made in the 1990s, PReP and CHRP. The PAPR specification provides the foundation for development of standard server computers. Various operating systems like Linux and IBM AIX rely on the PAPR interface to run on Power-based hardware. PAPR is Power.org's move toward what IBM did originally with PReP, in that it defines a common hardware definition and software/firmware platform under a set of requirements. In practice, the PAPR is an extension to the Open Firmware specification. Since 2013, extensions have been done by the OpenPOWER Foundation, which released a slightly reduced public version of the PAPR standard for running Linux on Power hardware (called LoPAPR In 2020, LoPAPR was renamed to Linux on Power Architecture Reference (LoPARwith the release of a new version. Contributing In July 2020, the d ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Coherent Accelerator Processor Interface
Coherent Accelerator Processor Interface (CAPI), is a high-speed processor expansion bus standard for use in large data center computers, initially designed to be layered on top of PCI Express, for directly connecting central processing units (CPUs) to external accelerators like graphics processing units (GPUs), ASICs, FPGAs or fast storage. It offers low latency, high speed, direct memory access connectivity between devices of different instruction set architectures. History The performance scaling traditionally associated with Moore's Law—dating back to 1965—began to taper off around 2004, as both Intel's Prescott architecture and IBM's Cell processor pushed toward a 4 GHz operating frequency. Here both projects ran into a thermal scaling wall, whereby heat extraction problems associated with further increases in operating frequency largely outweighed gains from shorter cycle times. Over the decade that followed, few commercial CPU products exceeded 4 GHz, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Tyan
Tyan Computer Corporation (泰安電腦科技股份有限公司; also known as Tyan Business Unit, or TBU) is a subsidiary of MiTAC International, and a manufacturer of computer motherboards, including models for both AMD and Intel processors. They develop and produce high-end server, SMP, and desktop barebones systems as well as provide design and production services to tier 1 global OEMs, and a number of other regional OEMs. Founding The company was founded in 1989 by Dr. T. Symon Chang, a veteran of IBM and Intel. At that time, Dr. Chang saw an empty space in the market in which there were no strong players for the SMP server space, and as such he founded Tyan in order to develop, produce and deliver such products, starting with a dual Intel Pentium-series motherboard as well as a number of other single processor motherboards all geared towards server applications. Since then, Tyan has produced a number of single and multi-processor (as well as multi-core) products using t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NVIDIA
Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to early-mid 2000s. Though unofficial, second letter capitalization of NVIDIA, i.e. nVidia, may be found within enthusiast communities and publications. ( ) is an American multinational technology company incorporated in Delaware and based in Santa Clara, California. It is a software and fabless company which designs graphics processing units (GPUs), application programming interface (APIs) for data science and high-performance computing as well as system on a chip units (SoCs) for the mobile computing and automotive market. Nvidia is a global leader in artificial intelligence hardware and software. Its professional line of GPUs are used in workstations for applications in such fields as architecture, engineering and construction, m ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NVLink
NVLink is a wire-based serial multi-lane near-range communications link developed by Nvidia. Unlike PCI Express, a device can consist of multiple NVLinks, and devices use mesh networking to communicate instead of a central hub. The protocol was first announced in March 2014 and uses a proprietary high-speed signaling interconnect (NVHS). Principle NVLink is a wire-based communications protocol for near-range semiconductor communications developed by Nvidia that can be used for data and control code transfers in processor systems between CPUs and GPUs and solely between GPUs. NVLink specifies a point-to-point connection with data rates of 20, 25 and 50 Gbit/s (v1.0/v2.0/v3.0 resp.) per differential pair. Eight differential pairs form a "sub-link" and two "sub-links", one for each direction, form a "link". The total data rate for a sub-link is 25 GByte/s and the total data rate for a link is 50 GByte/s. Each V100 GPU supports up to six links. Thus, each GPU is capable of suppor ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Firmware
In computing, firmware is a specific class of computer software that provides the low-level control for a device's specific hardware. Firmware, such as the BIOS of a personal computer, may contain basic functions of a device, and may provide hardware abstraction services to higher-level software such as operating systems. For less complex devices, firmware may act as the device's complete operating system, performing all control, monitoring and data manipulation functions. Typical examples of devices containing firmware are embedded systems (running embedded software), home and personal-use appliances, computers, and computer peripherals. Firmware is held in non-volatile memory devices such as ROM, EPROM, EEPROM, and flash memory. Updating firmware requires ROM integrated circuits to be physically replaced, or EPROM or flash memory to be reprogrammed through a special procedure. Some firmware memory devices are permanently installed and cannot be changed after manufact ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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