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MP6
The Rise mP6 was a superpipelined and superscalar microprocessor designed by Rise Technology to compete with the Intel Pentium line. History Rise Technology had spent 5 years developing a x86 compatible microprocessor, and finally introduced it in November 1998 as a low-cost, low-power alternative for the Super Socket 7 platform, that allowed for higher Front-side bus speeds than the previous Socket 7 and that made it possible for other CPU manufacturers to keep competing against Intel, that had moved to the Slot 1 platform. Design The mP6 made use of the MMX instruction set and had three MMX pipelines which allowed the CPU to execute up to three MMX instructions in a single cycle. Its three integer units made it possible to execute three integer instructions in a single cycle as well and the fully pipelined floating point unit could execute up to two floating-point instructions per cycle. To further improve the performance the core utilized branch prediction and a number of ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Rise Technology
Rise Technology was a short lived microprocessor manufacturer that produced the Intel x86 MMX compatible mP6 processor. The mP6 was a microprocessor that was designed to perform a smaller number of types of computer instructions so that it can operate at a higher speed (perform more millions of instructions per second, or MIPS). The Santa Clara, California based company was started by David Lin in 1993 with funding from 15 Taiwanese investors, including UMC, ACER and VIA Technologies. After multiple company restructurings, the mP6 was announced at the end of 1998 and went into small production in 1999. The device was meant for the low-end, low-power segment of laptop computers. Finding itself unable to compete in the computing market with the larger vendors (Intel and AMD), Rise re-targeted itself to set-top box A set-top box (STB), also known as a cable converter box, cable box, receiver, or simply box, and historically television decoder or a converter, is an informa ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Silicon Integrated Systems
Silicon Integrated Systems (SiS; ) is a company that manufactures, among other things, motherboard chipsets. The company was founded in 1987 in Hsinchu Science Park, Taiwan. Business In the late 1990s, SiS made the decision to invest in their own chip fabrication facilities. At the end of 1999, SiS acquired Rise Technology and its mP6 x86 core technology.Silicon Integrated Systems (SiS) acquired Hycon Technology on January 1, 2025. The acquisition involved SiS issuing 0.8713 shares for every Hycon share, totaling 27,755,080 shares. Mainboard chipsets One of the most famous chipsets produced by SiS was the late 486-age chipset 496/497 which supported PCI bus among older ISA- and VLB-buses. Mainboards using this chipset and equipped with CPUs such as the Intel 80486DX4, AMD 5x86 or Cyrix Cx5x86 processors had performance and compatibility comparable with early Intel Pentium systems in addition to a lower price. After this late success, SiS continued positioning itself as ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Super Socket 7
Super Socket 7, also referred to as Super 7, is a hardware-level extension of the Socket 7 Zero insertion force, ZIF socket specification for x86 processors. It was released in May 1998. Compatible motherboards and chipsets use a standard Socket 7 connection for the CPU, while adding certain features including a maximum 100 Megahertz, MHz front-side bus and support for Accelerated Graphics Port, AGP graphics cards. Super Socket 7 was used by Advanced Micro Devices, AMD AMD K6-2, K6-2 and AMD K6-III, K6-III processors, some of the final Cyrix M-II processors, some of the final Integrated Device Technology, IDT WinChip, WinChip 2 processors, and Rise Technology, Rise mP6 processors. It is backward compatibility, backward compatible with Socket 7 CPUs, meaning a Socket 7 CPU can be used with a Super Socket 7 motherboard, but a Super Socket 7 CPU cannot operate at full speed in a Socket 7 motherboard. Socket 5 CPUs are pin-compatible with Super Socket 7, but not all motherboards d ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel P5
The Pentium (also referred to as the i586 or P5 Pentium) is a microprocessor introduced by Intel on March 22, 1993. It is the first CPU using the Pentium, Pentium brand. Considered the fifth generation in the x86 (8086) compatible line of processors, succeeding the i486, its implementation and microarchitecture was internally called ''P5''. Like the Intel i486, the Pentium is instruction set compatible with the 32-bit i386. It uses a very similar microarchitecture to the i486, but was extended enough to implement a dual integer instruction pipelining, pipeline design, as well as a more advanced floating-point unit (FPU) that was noted to be ten times faster than its predecessor. The Pentium was succeeded by the Pentium Pro in November 1995. In October 1996, the Pentium MMX was introduced, complementing the same basic microarchitecture of the original Pentium with the MMX (instruction set), MMX instruction set, larger caches, and some other enhancements. Intel discontinued the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket 7
Socket 7 is a physical and electrical specification for an x86-style CPU socket on a personal computer motherboard. It was released in June 1995. The socket supersedes the earlier Socket 5, and accepts P5 Pentium microprocessors manufactured by Intel, as well as compatibles made by Cyrix/IBM, AMD, IDT and others. Socket 7 was the only socket that supported a wide range of CPUs from different manufacturers and a wide range of speeds. Differences between Socket 5 and Socket 7 are that Socket 7 has an extra pin and is designed to provide dual split rail voltage, as opposed to Socket 5's single voltage. However, not all motherboard manufacturers supported the dual voltage on their boards initially. Socket 7 is backwards compatible; a Socket 5 CPU can be inserted and used on a Socket 7 motherboard. Processors that used Socket 7 are the AMD K5 and K6, the Cyrix 6x86 and 6x86MX, the IDT WinChip, the Intel P5 Pentium (2.5–3.5 V, 75–200 MHz), the Pentium MMX (166–233 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel Pentium II
The Pentium II is a brand of sixth-generation Intel x86 microprocessors based on the P6 microarchitecture, introduced on May 7, 1997. It combined the ''P6'' microarchitecture seen on the Pentium Pro with the MMX instruction set of the Pentium MMX, and is the second processor using the Pentium brand. Containing 7.5 million transistors (27.4 million in the case of the mobile Dixon with 256 KB on-die L2 cache), the Pentium II featured an improved version of the first ''P6''-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pro's. In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based Celeron line of processors for low-end computers and the Intel Pentium II Xeon line for servers and workstations. The Celeron was characterized by a reduced or omitted (in some cases present but disabled) on-die full-speed L2 cache and a 66 MT/s FSB. The Xeon was ch ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MMX (instruction Set)
MMX is a ''single instruction, multiple data'' (SIMD) instruction set architecture designed by Intel, introduced on January 8, 1997 with its Pentium P5 (microarchitecture) based line of microprocessors, named "Pentium with MMX Technology". It developed out of a similar unit introduced on the Intel i860, and earlier the Intel i750 video pixel processor. MMX is a processor supplementary capability that is supported on IA-32 processors by Intel and other vendors . AMD also added MMX instruction set in its AMD K6, K6 processor. ''The New York Times'' described the initial push, including Super Bowl advertisements, as focused on "a new generation of glitzy multimedia products, including videophones and 3-D video games." MMX has subsequently been extended by several programs by Intel and others: 3DNow!, Streaming SIMD Extensions (SSE), and ongoing revisions of Advanced Vector Extensions (AVX). Overview Naming MMX is officially a meaningless initialism trademarked by Intel; unoffici ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Branch Predictor
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow in the instruction pipeline. Branch predictors play a critical role in achieving high performance in many modern pipelined microprocessor architectures. Two-way branching is usually implemented with a conditional jump instruction. A conditional jump can either be "taken" and jump to a different place in program memory, or it can be "not taken" and continue execution immediately after the conditional jump. It is not known for certain whether a conditional jump will be taken or not taken until the condition has been calculated and the conditional jump has passed the execution stage in the instruction pipeline (see fig. 1). Without branch prediction, the processor would have to wait until the conditional jump instruction has passed the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Data Dependency
A data dependency in computer science is a situation in which a program statement (instruction) refers to the data of a preceding statement. In compiler theory, the technique used to discover data dependencies among statements (or instructions) is called dependence analysis. Description Assuming statement S_1 and S_2, S_2 depends on S_1 if: :\left (S_1) \cap O(S_2)\right\cup \left (S_1) \cap I(S_2)\right\cup \left (S_1) \cap O(S_2)\right\neq \varnothing where: * I(S_i) is the set of memory locations read by * O(S_j) is the set of memory locations written by and * there is a feasible run-time execution path from S_1 to These conditions are called Bernstein's Conditions, named after Arthur J. Bernstein. Three cases exist: * Anti-dependence: I(S_1) \cap O(S_2) \neq \varnothing, S_1 \rightarrow S_2 and S_1 reads something before S_2 overwrites it * Flow (data) dependence: O(S_1) \cap I(S_2) \neq \varnothing, S_1 \rightarrow S_2 and S_1 writes before something read by S_2 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
WinChip
The WinChip series is a discontinued CPU electrical consumption, low-power Socket 7-based x86 central processing unit, processor that was designed by Centaur Technology and marketed by its parent company Integrated Device Technology, IDT. Overview Design The design of the WinChip was quite different from other processors of the time. Instead of a large gate count and die (integrated circuit), die area, IDT, using its experience from the RISC processor market, created a small and electrically efficient processor similar to the Intel 80486, 80486, because of its single Pipeline (computing), pipeline and Out of Order execution#In-order processors, in-order execution microarchitecture. It was of much simpler design than its Socket 7 competitors, such as AMD K5/AMD K6, K6, which were superscalar and based on dynamic translation to buffered micro-operations with advanced instruction reordering (Out of Order execution, out of order execution). Use WinChip was, in general, designed to per ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
CPU Caches
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with different instruction-specific and data-specific caches at level 1. The cache memory is typically implemented with static random-access memory (SRAM), in modern CPUs by far the largest part of them by chip area, but SRAM is not always used for all levels (of I- or D-cache), or even any level, sometimes some latter or all levels are implemented with eDRAM. Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) whi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Celeron
Celeron is a series of IA-32 and x86-64 computer microprocessor, microprocessors targeted at low-cost Personal computer, personal computers, manufactured by Intel from 1998 until 2023. The first Celeron-branded CPU was introduced on April 15, 1998, and was based on the Pentium II. Celeron-branded processors released from 2009 to 2023 are compatible with IA-32 software. They typically offer less performance per clock speed compared to flagship Intel CPU lines, such as the Pentium or Intel Core, Core brands. They often have less CPU cache, cache or intentionally disabled advanced features, with variable impact on performance. While some Celeron designs have achieved strong performance for their segment, the majority of the Celeron line has exhibited noticeably degraded performance. This has been the primary Market segmentation, justification for the higher cost of other Intel CPU brands versus the Celeron range. In September 2022, Intel announced that the Celeron brand, along wit ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
