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Hitachi SR2201
The Hitachi SR2201 was a distributed memory parallel system that was introduced in March 1996 by Hitachi. Its processor, the 150 MHz HARP-1E based on the PA-RISC 1.1 architecture, solved the cache miss penalty by pseudo vector processing (PVP). In PVP, data was loaded by prefetching to a special register bank, bypassing the cache. Each processor had a peak performance of 300 MFLOPS, giving the SR2201 a peak performance of 600 GFLOPS. Up to 2048 RISC processors could be connected via a high-speed three-dimensional crossbar network, which was able to transfer data at 300 MB/s over each link. In February 1996, two 1024-node systems were installed at the University of Tokyo and the University of Tsukuba is a List of national universities in Japan, national research university located in Tsukuba, Ibaraki Prefecture, Ibaraki, Japan. The university has 28 college clusters and schools with around 16,500 students (as of 2014). The main Tsukuba ca .... The latter was extended t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Distributed Memory
In computer science, distributed memory refers to a Multiprocessing, multiprocessor computer system in which each Central processing unit, processor has its own private Computer memory, memory. Computational tasks can only operate on local data, and if remote data are required, the computational task must communicate with one or more remote processors. In contrast, a Shared memory architecture, shared memory multiprocessor offers a single memory space used by all processors. Processors do not have to be aware where data resides, except that there may be performance penalties, and that race conditions are to be avoided. In a distributed memory system there is typically a processor, a memory, and some form of interconnection that allows programs on each processor to interact with each other. The interconnect can be organised with Network_topology#Point-to-point, point to point links or separate hardware can provide a switching network. The network topology is a key factor in deter ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Crossbar Switch
In electronics and telecommunications, a crossbar switch (cross-point switch, matrix switch) is a collection of switches arranged in a Matrix (mathematics), matrix configuration. A crossbar switch has multiple input and output lines that form a crossed pattern of interconnecting lines between which a connection may be established by closing a switch located at each intersection, the elements of the matrix. Originally, a crossbar switch consisted literally of crossing metal bars that provided the input and output paths. Later implementations achieved the same switching topology in solid-state electronics. The crossbar switch is one of the principal telephone exchange architectures, together with a rotary system, rotary switch, memory switch, and a crossover switch. General properties A crossbar switch is an assembly of individual switches between a set of inputs and a set of outputs. The switches are arranged in a matrix. If the crossbar switch has M inputs and N outputs, then a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Hitachi Products
() is a Japanese multinational conglomerate founded in 1910 and headquartered in Chiyoda, Tokyo. The company is active in various industries, including digital systems, power and renewable energy, railway systems, healthcare products, and financial systems. The company was founded as an electrical machinery manufacturing subsidiary of the Kuhara Mining Plant in Hitachi, Ibaraki by engineer Namihei Odaira in 1910. It began operating as an independent company under its current name in 1920. Hitachi is listed on the Tokyo Stock Exchange and is a key component of the Nikkei 225 and TOPIX Core30 indices. As of June 2024, it has a market capitalisation of 16.9 trillion yen, making it the fourth largest Japanese company by market value. In terms of global recognition, Hitachi was ranked 38th in the 2012 Fortune Global 500 and 129th in the 2012 Forbes Global 2000. Hitachi is a highly globalised conglomerate. In the fiscal year 2023, it generated approximately 61% of its total revenu ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ASCI Red
ASCI Red (also known as ASCI Option Red or TFLOPS) was the first computer built under the Accelerated Strategic Computing Initiative ( ASCI), the supercomputing initiative of the United States government created to help the maintenance of the United States nuclear arsenal after the 1992 moratorium on nuclear testing. ASCI Red was built by Intel and installed at Sandia National Laboratories in late 1996. The design was based on the Intel Paragon computer. The original goals to deliver a true teraflop machine by the end of 1996 that would be capable of running an ASCI application using all memory and nodes by September 1997 were met. It was used by the US government from the years of 1997 to 2005 and was the world's fastest supercomputer until late 2000. It was the first ASCI machine that the Department of Energy acquired, and also the first supercomputer to score above one teraflops on the LINPACK benchmark, a test that measures a computer's calculation speed. Later upgrade ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
TOP500
The TOP500 project ranks and details the 500 most powerful non-distributed computing, distributed computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year. The first of these updates always coincides with the International Supercomputing Conference in June, and the second is presented at the ACM/IEEE Supercomputing Conference in November. The project aims to provide a reliable basis for tracking and detecting trends in high-performance computing and bases rankings on HPL (benchmark), HPL benchmarks, a portable implementation of the high-performance LINPACK benchmarks, LINPACK benchmark written in Fortran for Distributed memory, distributed-memory computers. The most recent edition of TOP500 was published in June 2025 as the 65th edition of TOP500, while the next edition of TOP500 will be published in November 2025 as the 66th edition of TOP500. As of June 2025, the United States' El Capitan (supercomputer), El ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Numerical Wind Tunnel
Numerical Wind Tunnel (数値風洞) was an early implementation of the vector parallel architecture developed in a joint project between National Aerospace Laboratory of Japan and Fujitsu. It was the first supercomputer with a sustained performance of close to 100 Gflop/s for a wide range of fluid dynamics application programs. It stood out at the top of the TOP500 during 1993-1996. With 140 cores, the Numerical Wind Tunnel reached a Rmax of 124.0 GFlop/s and a Rpeak''Rpeak'' – This is the theoretical peak performance of the system. Measured in Pflops. of 235.8 GFlop/s in November 1993. It consisted of parallel connected 166 vector processor In computing, a vector processor or array processor is a central processing unit (CPU) that implements an instruction set where its instructions are designed to operate efficiently and effectively on large one-dimensional arrays of data called ...s with a gate delay as low as 60 ps in the Ga-As chips. The resulting cycle time was 9 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
LINPACK
LINPACK is a software library for performing numerical linear algebra on digital computers. It was written in Fortran by Jack Dongarra, Jim Bunch, Cleve Moler, and Gilbert Stewart, and was intended for use on supercomputers in the 1970s and early 1980s. It has been largely superseded by LAPACK, which runs more efficiently on modern architectures. LINPACK makes use of the BLAS (Basic Linear Algebra Subprograms) libraries for performing basic vector and matrix operations. The LINPACK benchmarks appeared initially as part of the LINPACK user's manual. The parallel LINPACK benchmark implementation called HPL (High Performance Linpack) is used to benchmark and rank supercomputers for the TOP500 The TOP500 project ranks and details the 500 most powerful non-distributed computing, distributed computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year. The first of these ... list. World's most powerful com ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
University Of Tsukuba
is a List of national universities in Japan, national research university located in Tsukuba, Ibaraki Prefecture, Ibaraki, Japan. The university has 28 college clusters and schools with around 16,500 students (as of 2014). The main Tsukuba campus covers an area of 258 hectares (636 acres), making it the second largest single campus in Japan. The university has a branch campus in Bunkyō, Bunkyo-ku, Tokyo, offering graduate programs for working adults in the capital and managing K-12 schools in Tokyo that are attached to the university. Three Nobel Prize laurates have taught at the university, Leo Esaki, Hideki Shirakawa and Sin-Itiro Tomonaga. Apart from them, Satoshi Ōmura studied as an audit student. History The University of Tsukuba can trace its roots back to , a normal school established in 1872 to educate primary and secondary teachers. The school was promoted to a university in 1929, as Tokyo University of Literature and Science (東京文理科大学, ''Tōkyō ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
University Of Tokyo
The University of Tokyo (, abbreviated as in Japanese and UTokyo in English) is a public research university in Bunkyō, Tokyo, Japan. Founded in 1877 as the nation's first modern university by the merger of several pre-westernisation era institutions, its direct precursors include the '' Tenmongata'', founded in 1684, and the Shōheizaka Institute. Although established under its current name, the university was renamed in 1886 and was further retitled to distinguish it from other Imperial Universities established later. It served under this name until the official dissolution of the Empire of Japan in 1947, when it reverted to its original name. Today, the university consists of 10 faculties, 15 graduate schools, and 11 affiliated research institutes. As of 2023, it has a total of 13,974 undergraduate students and 14,258 graduate students. The majority of the university's educational and research facilities are concentrated within its three main Tokyo campuses: Hongō, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Reduced Instruction Set Computer
In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions perform simpler operations. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler to achieve given simpler instructions. The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load–store architecture in which the code for the register-register instructions (for performin ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Parallel Computer
Parallel computing is a type of computation in which many calculations or processes are carried out simultaneously. Large problems can often be divided into smaller ones, which can then be solved at the same time. There are several different forms of parallel computing: bit-level, instruction-level, data, and task parallelism. Parallelism has long been employed in high-performance computing, but has gained broader interest due to the physical constraints preventing frequency scaling.S.V. Adve ''et al.'' (November 2008)"Parallel Computing Research at Illinois: The UPCRC Agenda" (PDF). Parallel@Illinois, University of Illinois at Urbana-Champaign. "The main techniques for these performance benefits—increased clock frequency and smarter but increasingly complex architectures—are now hitting the so-called power wall. The computer industry has accepted that future performance increases must largely come from increasing the number of processors (or cores) on a die, rather than mak ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Memory Bank
A memory bank is a logical unit of storage in electronics, which is hardware-dependent. In a computer, the memory bank may be determined by the memory controller along with physical organization of the hardware memory slots. In a typical synchronous dynamic random-access memory (SDRAM) or double data rate SDRAM (DDR SDRAM), a bank consists of multiple rows and columns of storage units, and is usually spread out across several chips. In a single read or write operation, only one bank is accessed, therefore the number of bits in a column or a row, per bank and per chip, equals the memory bus width in bits (single channel). The size of a bank is further determined by the number of bits in a column and a row, per chip, multiplied by the number of chips in a bank. Some computers have several identical memory banks of RAM, and use bank switching to switch between them. Harvard architecture computers have (at least) two very different banks of memory, one for program storage and anot ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
