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DNA-OS
DNA-OS is a French-made operating system to supersede MutekA, an obsolete operating system, while still providing POSIX thread API. As said on thSoCLib website "It is a kernel-mode lightweight operating system for Multiprocessor System on a Chip. It is built on top of a thin HAL to ease porting on new platforms and processor architecture. DNA/OS does not support virtual memory." DNA-OS is a layered microkernel operating system, written in C99, released under the GNU GPLv3 license. Target hardware / software * ARM7, ARM9, Cortex A8/ A9 * MIPS * Micro Blaze * SparcV8 * NiOS OS flavours * SMP (Symmetric multiprocessing) * DS (Distributed Scheduling) Associated libraries * Native POSIX Threads * Newlib Newlib is a C standard library implementation intended for use on embedded systems. It is a conglomeration of several library parts, all under free software licenses that make them easily usable on embedded products. It was created by Cygnus ...c References {{R ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of Operating Systems
This is a list of operating systems. Computer operating systems can be categorized by technology, ownership, licensing, working state, usage, and by many other characteristics. In practice, many of these groupings may overlap. Criteria for inclusion is notability, as shown either through an existing Wikipedia article or citation to a reliable source. Proprietary Acorn Computers * Arthur * ARX * MOS * RISC iX * RISC OS Amazon * Fire OS Amiga Inc. * AmigaOS ** AmigaOS 1.0-3.9 (Motorola 68000) ** AmigaOS 4 (PowerPC) * Amiga Unix (a.k.a. Amix) Amstrad * AMSDOS * Contiki * CP/M 2.2 * CP/M Plus * SymbOS Apple * Apple II ** Apple DOS ** Apple Pascal ** Apex (Colorado School of Mines) ** Apple ProDOS, ProDOS ** Apple GS/OS, GS/OS ** GNO/ME ** Contiki * Apple III ** Apple SOS * Apple Lisa * Mac ** Classic Mac OS ** A/UX (UNIX System V with BSD extensions) ** Copland ** MkLinux ** Pink ** Rhapsody ** macOS (formerly Mac OS X and OS X) *** macOS Server (formerly Mac OS X S ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Microkernel
In computer science, a microkernel (often abbreviated as μ-kernel) is the near-minimum amount of software that can provide the mechanisms needed to implement an operating system (OS). These mechanisms include low-level address space management, thread (computing), thread management, and inter-process communication (IPC). If the hardware provides multiple Protection ring, rings or CPU modes, the microkernel may be the only software executing at the most privileged level, which is generally referred to as kernel mode, supervisor or kernel mode. Traditional operating system functions, such as device drivers, protocol stacks and file systems, are typically removed from the microkernel itself and are instead run in user space. In terms of the source code size, microkernels are often smaller than monolithic kernels. The MINIX 3 microkernel, for example, has only approximately 12,000 lines of code. History Microkernels trace their roots back to Danish computer pioneer Per Brinch ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GPLv3
The GNU General Public Licenses (GNU GPL or simply GPL) are a series of widely used free software licenses, or ''copyleft'' licenses, that guarantee end users the freedom to run, study, share, or modify the software. The GPL was the first copyleft license available for general use. It was originally written by Richard Stallman, the founder of the Free Software Foundation (FSF), for the GNU Project. The license grants the recipients of a computer program the rights of the Free Software Definition. The licenses in the GPL series are all copyleft licenses, which means that any derivative work must be distributed under the same or equivalent license terms. The GPL is more restrictive than the GNU Lesser General Public License, and even more distinct from the more widely used permissive software licenses such as BSD, MIT, and Apache. Historically, the GPL license family has been one of the most popular software licenses in the free and open-source software (FOSS) domain. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM7
ARM7 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. The ARM7 core family consists of ARM700, ARM710, ARM7DI, ARM710a, ARM720T, ARM740T, ARM710T, ARM7TDMI, ARM7TDMI-S, ARM7EJ-S. The ARM7TDMI and ARM7TDMI-S were the most popular cores of the family. ARM7 cores were released from 1993 to 2001 and no longer recommended for new IC designs; newer alternatives are ARM Cortex-M cores. Overview This generation introduced the Thumb 16-bit instruction set providing improved code density compared to previous designs. The most widely used ARM7 designs implement the ARMv4T architecture, but some implement ARMv3 or ARMv5TEJ. ARM7TDMI has 37 registers (31 GPR and 6 SPR). All these designs use a Von Neumann architecture, thus the few versions containing a cache do not separate data and instruction caches. Some ARM7 cores are obsolete. One historically significant model, the ARM7DI"ARM7DI Data Sheet"; Document Number ARM DDI 0027D; Issued: ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM9
ARM9 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. The ARM9 core family consists of ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, ARM996HS. ARM9 cores were released from 1998 to 2006, and no longer recommended for new IC designs; newer alternatives are ARM Cortex-M cores. Overview With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a (modified; meaning split cache) Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed. Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories. There are two subfamilies, implementing different ARM architecture versions. Differences from ARM7 cores Key improvements over ARM7 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A8
The ARM Cortex-A8 is a 32-bit processor core licensed by ARM Holdings implementing the ARM architecture, ARMv7-A architecture. Compared to the ARM11, the Cortex-A8 is a dual-issue superscalar processor, superscalar design, achieving roughly twice the instructions per cycle. The Cortex-A8 was the first Cortex design to be adopted on a large scale in consumer devices. Features Key features of the Cortex-A8 core are: * Frequency from 600 MHz to 1 GHz and above * Superscalar dual-issue microarchitecture * ARM NEON, NEON SIMD instruction set extension * 13-stage integer instruction pipeline, pipeline and 10-stage NEON pipeline * VFPv3 floating-point unit * Thumb-2 instruction set encoding * Jazelle RCT (also known as ThumbEE instruction set) * Advanced branch predictor, branch prediction unit with >95% accuracy * Integrated level 2 Cache (0–4 MiB) * 2.0 Dhrystone, DMIPS/MHz Chips Several system-on-a-chip, system-on-chips (SoC) have implemented the Cortex-A8 core, incl ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A9
The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set. It was introduced in 2007. Features Key features of the Cortex-A9 core are: * out-of-order execution, Out-of-order speculative execution, speculative issue superscalar execution 8-stage instruction pipeline, pipeline giving 8.50 Dhrystone, DMIPS/MHz/core. * ARM NEON, NEON SIMD instruction set extension performing up to 16 operations per instruction (optional). * High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional). * Thumb-2 instruction set encoding reduces the size of programs with little impact on performance. * TrustZone security extensions. * Jazelle DBX support for Java execution. * Jazelle RCT for JIT compilation. * Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution. * L2 cache controller (0–4 MB). * Multi- ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Stanford MIPS
MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called reduced instruction set computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessy was awarded the IEEE John von Neumann Medal in 2000 by the Institute of Electrical and Electronics Engineers (IEEE) (shared with David Patterson (computer scientist), David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, the Seymour Cray Computer Engineering Award ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nios II
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control. Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios, introduced in 2000. Intel announced the discontinuation of Nios II in 2023, with its successor being Nios V, based on the RISC-V architecture. Key features Like the original Nios, the Nios II architecture is a RISC soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full 32-bit design: * 32 general-purpose 32-bit registers, * Full 32-bit instruction set, data path, and address space, * Single-instruction 32 × 32 multiply and divide ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Symmetric Multiprocessing
Symmetric multiprocessing or shared-memory multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single, shared main memory, have full access to all input and output devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Most multiprocessor systems today use an SMP architecture. In the case of multi-core processors, the SMP architecture applies to the cores, treating them as separate processors. Professor John D. Kubiatowicz considers traditionally SMP systems to contain processors without caches. Culler and Pal-Singh in their 1998 book "Parallel Computer Architecture: A Hardware/Software Approach" mention: "The term SMP is widely used but causes a bit of confusion. ..The more precise description of what is intended by SMP is a shared memory multiprocessor where the cost of accessing a memory location ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
