Microcode is "a technique that imposes an interpreter between the
hardware and the architectural level of a computer". As such, the
microcode is a layer of hardware-level instructions that implement
higher-level machine code instructions or internal state machine
sequencing in many digital processing elements.
Microcode is used in
general-purpose central processing units, as well as in more
specialized processors such as microcontrollers, digital signal
processors, channel controllers, disk controllers, network interface
controllers, network processors, graphics processing units, and in
Microcode typically resides in special high-speed memory and
translates machine instructions, state machine data or other input
into sequences of detailed circuit-level operations. It separates the
machine instructions from the underlying electronics so that
instructions can be designed and altered more freely. It also
facilitates the building of complex multi-step instructions, while
reducing the complexity of computer circuits. Writing microcode is
often called microprogramming and the microcode in a particular
processor implementation is sometimes called a microprogram.
More extensive microcoding allows small and simple microarchitectures
to emulate more powerful architectures with wider word length, more
execution units and so on, which is a relatively simple way to achieve
software compatibility between different products in a processor
Some hardware vendors, especially IBM, use the term microcode as a
synonym for firmware. In that way, all code within a device is termed
microcode regardless of it being microcode or machine code; for
example, hard disk drives are said to have their microcode updated,
though they typically contain both microcode and firmware.
5.1 Horizontal microcode
5.2 Vertical microcode
6 Writable control store
7 Comparison to VLIW and RISC
8 See also
11 Further reading
12 External links
When compared to normal application programs, the elements composing a
microprogram exist on a lower conceptual level. To avoid confusion,
each microprogram-related element is differentiated by the micro
prefix: microinstruction, microassembler, microprogrammer,
Engineers normally write the microcode during the design phase of a
processor, storing it in a read-only memory (ROM) or programmable
logic array (PLA) structure, or in a combination of both.
However, machines also exist that have some or all microcode stored in
SRAM or flash memory. This is traditionally denoted as writeable
control store in the context of computers, which can be either
read-only or read-write memory. In the latter case, the CPU
initialization process loads microcode into the control store from
another storage medium, with the possibility of altering the microcode
to correct bugs in the instruction set, or to implement new machine
Complex digital processors may also employ more than one (possibly
microcode-based) control unit in order to delegate sub-tasks that must
be performed essentially asynchronously in parallel. A high-level
programmer, or even an assembly programmer, does not normally see or
change microcode. Unlike machine code, which often retains some
backward compatibility among different processors in a family,
microcode only runs on the exact electronic circuitry for which it is
designed, as it constitutes an inherent part of the particular
processor design itself.
Microprograms consist of series of microinstructions, which control
the CPU at a very fundamental level of hardware circuitry. For
example, a single typical horizontal microinstruction might specify
the following operations:
Connect register 1 to the A side of the ALU
Connect register 7 to the B side of the ALU
Set the ALU to perform two's-complement addition
Set the ALU's carry input to zero
Store the result value in register 8
Update the condition codes from the ALU status flags (negative, zero,
overflow, and carry)
Microjump to microPC nnn for the next microinstruction
To simultaneously control all processor's features in one cycle, the
microinstruction is often wider than 50 bits; e.g., 128 bits on a
360/85 with an emulator feature. Microprograms are carefully designed
and optimized for the fastest possible execution, as a slow
microprogram would result in a slow machine instruction and degraded
performance for related application programs that use such
Microcode was originally developed as a simpler method of developing
the control logic for a computer. Initially, CPU instruction sets were
hardwired. Each step needed to fetch, decode, and execute the machine
instructions (including any operand address calculations, reads, and
writes) was controlled directly by combinational logic and rather
minimal sequential state machine circuitry. While very efficient, the
need for powerful instruction sets with multi-step addressing and
complex operations (see below) made such hard-wired processors
difficult to design and debug; highly encoded and varied-length
instructions can contribute to this as well, especially when very
irregular encodings are used.
Microcode simplified the job by allowing much of the processor's
behaviour and programming model to be defined via microprogram
routines rather than by dedicated circuitry. Even late in the design
process, microcode could easily be changed, whereas hard-wired CPU
designs were very cumbersome to change. Thus, this greatly facilitated
From the 1940s to the late 1970s, a large portion of programming was
done in assembly language; higher-level instructions mean greater
programmer productivity, so an important advantage of microcode was
the relative ease by which powerful machine instructions can be
defined. The ultimate extension of this are "Directly Executable High
Level Language" designs, in which each statement of a high-level
language such as
PL/I is entirely and directly executed by microcode,
without compilation. The
IBM Future Systems project and Data General
Fountainhead Processor are examples of this. During the 1970s, CPU
speeds grew more quickly than memory speeds and numerous techniques
such as memory block transfer, memory pre-fetch and multi-level caches
were used to alleviate this. High-level machine instructions, made
possible by microcode, helped further, as fewer more complex machine
instructions require less memory bandwidth. For example, an operation
on a character string can be done as a single machine instruction,
thus avoiding multiple instruction fetches.
Architectures with instruction sets implemented by complex
microprograms included the
System/360 and Digital Equipment
Corporation VAX. The approach of increasingly complex
microcode-implemented instruction sets was later called CISC. An
alternate approach, used in many microprocessors, is to use PLAs or
ROMs (instead of combinational logic) mainly for instruction decoding,
and let a simple state machine (without much, or any, microcode) do
most of the sequencing. The
MOS Technology 6502
MOS Technology 6502 is an example of a
microprocessor using a PLA for instruction decode and sequencing. The
PLA is visible in photomicrographs of the chip, and its operation
can be seen in the transistor-level simulation.
Microprogramming is still used in modern CPU designs. In some cases,
after the microcode is debugged in simulation, logic functions are
substituted for the control store. Logic functions
are often faster and less expensive than the equivalent microprogram
A processor's microprograms operate on a more primitive, totally
different, and much more hardware-oriented architecture than the
assembly instructions visible to normal programmers. In coordination
with the hardware, the microcode implements the programmer-visible
architecture. The underlying hardware need not have a fixed
relationship to the visible architecture. This makes it easier to
implement a given instruction set architecture on a wide variety of
underlying hardware micro-architectures.
System/360 has a 3
2-bit architecture with 16 general-purpose
registers, but most of the
System/360 implementations actually use
hardware that implemented a much simpler underlying microarchitecture;
for example, the
System/360 Model 30 has
8-bit data paths to the
arithmetic logic unit (ALU) and main memory and implemented the
general-purpose registers in a special unit of higher-speed core
memory, and the
System/360 Model 40 has
8-bit data paths to the ALU
16-bit data paths to main memory and also implemented the
general-purpose registers in a special unit of higher-speed core
memory. The Model 50 has full
32-bit data paths and implements the
general-purpose registers in a special unit of higher-speed core
memory. The Model 65 through the Model 195 have larger data paths
and implement the general-purpose registers in faster transistor
circuits. In this way, microprogramming enabled IBM
to design many
System/360 models with substantially different hardware
and spanning a wide range of cost and performance, while making them
all architecturally compatible. This dramatically reduces the number
of unique system software programs that must be written for each
A similar approach was used by
Digital Equipment Corporation
Digital Equipment Corporation (DEC) in
VAX family of computers. As a result, different
use different microarchitectures, yet the programmer-visible
architecture does not change.
Microprogramming also reduces the cost of field changes to correct
defects (bugs) in the processor; a bug can often be fixed by replacing
a portion of the microprogram rather than by changes being made to
hardware logic and wiring.
In 1947, the design of the MIT Whirlwind introduced the concept of a
control store as a way to simplify computer design and move beyond ad
hoc methods. The control store is a diode matrix: a two-dimensional
lattice, where one dimension accepts "control time pulses" from the
CPU's internal clock, and the other connects to control signals on
gates and other circuits. A "pulse distributor" takes the pulses
generated by the CPU clock and breaks them up into eight separate time
pulses, each of which activates a different row of the lattice. When
the row is activated, it activates the control signals connected to
Described another way, the signals transmitted by the control store
are being played much like a player piano roll. That is, they are
controlled by a sequence of very wide words constructed of bits, and
they are "played" sequentially. In a control store, however, the
"song" is short and repeated continuously.
Maurice Wilkes enhanced this concept by adding conditional
execution, a concept akin to a conditional in computer software. His
initial implementation consisted of a pair of matrices: the first one
generated signals in the manner of the Whirlwind control store, while
the second matrix selected which row of signals (the microprogram
instruction word, so to speak) to invoke on the next cycle.
Conditionals were implemented by providing a way that a single line in
the control store could choose from alternatives in the second matrix.
This made the control signals conditional on the detected internal
signal. Wilkes coined the term microprogramming to describe this
feature and distinguish it from a simple control store.
American Megatrends BIOS showing a "
Intel CPU uCode Loading Error"
after a failed attempt to upload microcode patches into the CPU.
In common with many other complex mechanical devices, Charles
Babbage's analytical engine uses banks of cams to control each
operation. That is, it has a read-only control store. As such, it
deserves to be recognised as the first microprogrammed computer to be
designed, although it had not been implemented in hardware until
The EMIDEC 1100 reputedly uses a hard-wired control store
consisting of wires threaded through ferrite cores, known as "the
Most models of the
System/360 series are microprogrammed:
The Model 25 is unique among
System/360 models in using the top
16 K bytes of core storage to hold the control storage for the
microprogram. The 2025 uses a
16-bit microarchitecture with seven
control words (or microinstructions). At power up, or full system
reset, the microcode is loaded from the card reader. The
emulation for this model is loaded this way.
The Model 30, the slowest model in the line, uses an 8-bit
microarchitecture with only a few hardware registers; everything that
the programmer saw is emulated by the microprogram. The microcode for
this model is also held on special punched cards, which are stored
inside the machine in a dedicated reader per card, called "CROS" units
(Capacitor Read-Only Storage). A second CROS reader is installed for
machines ordered with 1620 emulation.
The Model 40 uses 56-bit control words. The 2040 box implements both
System/360 main processor and the multiplex channel (the I/O
processor). This model uses "TROS" dedicated readers similar to "CROS"
units, but with an inductive pickup (Transformer Read-only Store).
The Model 50 has two internal datapaths which operated in parallel: a
32-bit datapath used for arithmetic operations, and an
8-bit data path
used in some logical operations. The control store uses 90-bit
The Model 85 has separate instruction fetch (I-unit) and execution
(E-unit) to provide high performance. The I-unit is hardware
controlled. The E-unit is microprogrammed; the control words are 108
bits wide on a basic 360/85 and wider if an emulator feature is
NCR 315 is microprogrammed with hand wired ferrite cores (a ROM)
pulsed by a sequencer with conditional execution. Wires routed through
the cores are enabled for various data and logic elements in the
Digital Equipment Corporation
Digital Equipment Corporation
PDP-11 processors, with the
exception of the PDP-11/20, are microprogrammed.
Data General Eclipse minicomputers are microprogrammed. The task
of writing microcode for the Eclipse MV/8000 is detailed in the
Pulitzer Prize-winning book titled The Soul of a New Machine.
Many systems from Burroughs are microprogrammed:
The B700 "microprocessor" execute application-level opcodes using
16-bit microinstructions stored in main memory; each of
these is either a register-load operation or mapped to a single 56-bit
"nanocode" instruction stored in read-only memory. This allows
comparatively simple hardware to act either as a mainframe peripheral
controller or to be packaged as a standalone computer.
B1700 is implemented with radically different hardware including
bit-addressable main memory but has a similar multi-layer
organisation. The operating system preloads the interpreter for
whatever language is required. These interpreters present different
virtual machines for COBOL, Fortran, etc.
Microdata produced computers in which the microcode is accessible to
the user; this allows the creation of custom assembler level
instructions. Microdata's Reality operating system design makes
extensive use of this capability.
The Xerox Alto workstation used a microcoded design but, unlike many
computers, the microcode engine is not hidden from the programmer in a
layered design. Applications take advantage of this to accelerate
The Nintendo 64's
Reality Coprocessor (RCP), which serves as the
console's graphics processing unit and audio processor, utilizes
microcode; it is possible to implement new effects or tweak the
processor to achieve the desired output. Some notable examples of
custom RCP microcode include the high-resolution graphics, particle
engines, and unlimited draw distances found in Factor 5's Indiana
Jones and the Infernal Machine, Star Wars: Rogue Squadron, and Star
Wars: Battle for Naboo; and the full motion video playback
found in Angel Studios' Resident Evil 2.
Further information on
Nintendo 64 microcode:
Nintendo 64 programming
Nintendo 64 Game Pak
The VU0 and VU1 vector units in the
PlayStation 2 are
microprogrammable; in fact, VU1 is only accessible via microcode for
the first several generations of the SDK.
The MicroCore Labs MCL86 and MCL51 are examples of highly encoded
"vertical" microsequencer implementations of the
Intel 8086/8088 and
Each microinstruction in a microprogram provides the bits that control
the functional elements that internally compose a CPU. The advantage
over a hard-wired CPU is that internal CPU control becomes a
specialized form of a computer program.
Microcode thus transforms a
complex electronic design challenge (the control of a CPU) into a less
complex programming challenge. To take advantage of this, a CPU is
divided into several parts:
A microsequencer picks the next word of the control store. A sequencer
is mostly a counter, but usually also has some way to jump to a
different part of the control store depending on some data, usually
data from the instruction register and always some part of the control
store. The simplest sequencer is just a register loaded from a few
bits of the control store.
A register set is a fast memory containing the data of the central
processing unit. It may include the program counter, stack pointer,
and other numbers that are not easily accessible to the application
programmer. Often the register set is a triple-ported register file;
that is, two registers can be read, and a third written at the same
An arithmetic and logic unit performs calculations, usually addition,
logical negation, a right shift, and logical AND. It often performs
other functions, as well.
There may also be a memory address register and a memory data
register, used to access the main computer storage. Together, these
elements form an "execution unit". Most modern CPUs have several
execution units. Even simple computers usually have one unit to read
and write memory, and another to execute user code. These elements
could often be brought together as a single chip. This chip comes in a
fixed width that would form a "slice" through the execution unit.
These are known as "bit slice" chips. The
AMD Am2900 family is one of
the best known examples of bit slice elements. The parts of the
execution units and the execution units themselves are interconnected
by a bundle of wires called a bus.
Programmers develop microprograms, using basic software tools. A
microassembler allows a programmer to define the table of bits
symbolically. Because of its close relationship to the underlying
architecture, "microcode has several properties that make it difficult
to generate using a compiler." A simulator program is intended to
execute the bits in the same way as the electronics, and allows much
more freedom to debug the microprogram. After the microprogram is
finalized, and extensively tested, it is sometimes used as the input
to a computer program that constructs logic to produce the same
data. This program is similar to those used to
optimize a programmable logic array. Even without fully optimal logic,
heuristically optimized logic can vastly reduce the number of
transistors from the number required for a ROM control store. This
reduces the cost of producing, and the electricity consumed by, a CPU.
Microcode can be characterized as horizontal or vertical, referring
primarily to whether each microinstruction controls CPU elements with
little or no decoding (horizontal microcode)[a] or requires extensive
decoding by combinatorial logic before doing so (vertical microcode).
Consequently, each horizontal microinstruction is wider (contains more
bits) and occupies more storage space than a vertical
"Horizontal microcode has several discrete micro-operations that are
combined in a single microinstruction for simultaneous operation."
Horizontal microcode is typically contained in a fairly wide control
store; it is not uncommon for each word to be 108 bits or more. On
each tick of a sequencer clock a microcode word is read, decoded, and
used to control the functional elements that make up the CPU.
In a typical implementation a horizontal microprogram word comprises
fairly tightly defined groups of bits. For example, one simple
arrangement might be:
Register source A
Register source B
Arithmetic and logic unit
Arithmetic and logic unit operation
Type of jump
For this type of micromachine to implement a JUMP instruction with the
address following the opcode, the microcode might require two clock
ticks. The engineer designing it would write microassembler source
code looking something like this:
# Any line starting with a number-sign is a comment
# This is just a label, the ordinary way assemblers symbolically
# memory address.
# To prepare for the next instruction, the instruction-decode
microcode has already
# moved the program counter to the memory address register. This
# the target address of the jump instruction from the memory
word following the
# jump opcode, by copying from the memory data register to the
memory address register.
# This gives the memory system two clock ticks to fetch the next
# instruction to the memory data register for use by the
# The sequencer instruction "next" means just add 1 to the
control word address.
MDR, NONE, MAR, COPY, NEXT, NONE
# This places the address of the next instruction into the PC.
# This gives the memory system a clock tick to finish the fetch
started on the
# previous microinstruction.
# The sequencer instruction is to jump to the start of the
MAR, 1, PC, ADD, JMP, InstructionDecode
# The instruction decode is not shown, because it is usually a
mess, very particular
# to the exact processor being emulated. Even this example is
# Many CPUs have several ways to calculate the address, rather
than just fetching
# it from the word following the op-code. Therefore, rather than
# jump instruction, those CPUs have a family of related jump
For each tick it is common to find that only some portions of the CPU
are used, with the remaining groups of bits in the microinstruction
being no-ops. With careful design of hardware and microcode, this
property can be exploited to parallelise operations that use different
areas of the CPU; for example, in the case above, the ALU is not
required during the first tick, so it could potentially be used to
complete an earlier arithmetic instruction.
In vertical microcode, each microinstruction is significantly
encoded – that is, the bit fields generally pass through
intermediate combinatory logic that, in turn, generates the actual
control and sequencing signals for internal CPU elements (ALU,
registers, etc.). This is in contrast with horizontal microcode, in
which the bit fields themselves either directly produce the control
and sequencing signals or are only minimally encoded. Consequently,
vertical microcode requires smaller instruction lengths and less
storage, but requires more time to decode, resulting in a slower CPU
Some vertical microcode is just the assembly language of a simple
conventional computer that is emulating a more complex computer. Some
processors, such as
DEC Alpha processors and the CMOS microprocessors
System/390 mainframes and z/Architecture mainframes, have
PALcode (the term used on Alpha processors) or millicode (the term
IBM mainframe microprocessors). This is a form of machine
code, with access to special registers and other hardware resources
not available to regular machine code, used to implement some
instructions and other functions, such as page table walks on Alpha
Another form of vertical microcode has two fields:
The field select selects which part of the CPU will be controlled by
this word of the control store. The field value actually controls that
part of the CPU. With this type of microcode, a designer explicitly
chooses to make a slower CPU to save money by reducing the unused bits
in the control store; however, the reduced complexity may increase the
CPU's clock frequency, which lessens the effect of an increased number
of cycles per instruction.
As transistors became cheaper, horizontal microcode came to dominate
the design of CPUs using microcode, with vertical microcode being used
When both vertical and horizontal microcode are used, the horizontal
microcode may be referred to as nanocode or picocode.
Writable control store
Main article: Writable control store
A few computers were built using "writable microcode". In this design,
rather than storing the microcode in ROM or hard-wired logic, the
microcode is stored in a RAM called a writable control store or WCS.
Such a computer is sometimes called a writable instruction set
computer or WISC.
Many experimental prototype computers use writable control stores;
there are also commercial machines that use writable microcode, such
as the Burroughs Small Systems, early Xerox workstations, the DEC VAX
8800 ("Nautilus") family, the
Symbolics L- and G-machines, a number of
System/370 implementations, some DEC PDP-10
machines, and the
Data General Eclipse MV/8000.
Many more machines offer user-programmable writable control stores as
an option, including the HP 2100, DEC PDP-11/60 and Varian Data
Machines V-70 series minicomputers. The
System/370 includes a
facility called Initial-Microprogram Load (IML or IMPL) that can
be invoked from the console, as part of power-on reset (POR) or from
another processor in a tightly coupled multiprocessor complex.
Some commercial machines, for example
IBM 360/85, have both a
read-only storage and a writable control store for microcode.
WCS offers several advantages including the ease of patching the
microprogram and, for certain hardware generations, faster access than
ROMs can provide. User-programmable WCS allows the user to optimize
the machine for specific purposes.
Starting with the
Pentium Pro in 1995, several
Intel x86 CPUs have
writable microcode. This, for example, has allowed bugs in the
Intel Core 2 and
Xeon microcodes to be fixed by patching
their microprograms, rather than requiring the entire chips to be
replaced. A second prominent example is the set of microcode patches
Intel offered for improving the capabilities of processor
architectures of up to nearly 10 years in age in the progress of
counter fighting the serious Spectre and Meltdown security dangers as
went really public in start of 2018. A microcode update can be
installed by Linux, FreeBSD, Microsoft Windows, or the
Comparison to VLIW and RISC
The design trend toward heavily microcoded processors with complex
instructions began in the early 1960s and continued until roughly the
mid-1980s. At that point the
RISC design philosophy started becoming
A CPU that uses microcode generally takes several clock cycles to
execute a single instruction, one clock cycle for each step in the
microprogram for that instruction. Some CISC processors include
instructions that can take a very long time to execute. Such
variations interfere with both interrupt latency and, what is far more
important in modern systems, pipelining.
When designing a new processor, a hardwired control
RISC has the
following advantages over microcoded CISC:
Programming has largely moved away from assembly level, so it's no
longer worthwhile to provide complex instructions for productivity
Simpler instruction sets allow direct execution by hardware, avoiding
the performance penalty of microcoded execution.
Analysis shows complex instructions are rarely used, hence the machine
resources devoted to them are largely wasted.
The machine resources devoted to rarely used complex instructions are
better used for expediting performance of simpler, commonly used
Complex microcoded instructions may require many clock cycles that
vary, and are difficult to pipeline for increased performance.
There are counterpoints as well:
The complex instructions in heavily microcoded implementations may not
take much extra machine resources, except for microcode space. For
instance, the same ALU is often used to calculate an effective address
as well as computing the result from the actual operands (e.g., the
original Z80, 8086, and others).
The simpler non-
RISC instructions (i.e., involving direct memory
operands) are frequently used by modern compilers. Even immediate to
stack (i.e., memory result) arithmetic operations are commonly
employed. Although such memory operations, often with varying length
encodings, are more difficult to pipeline, it is still fully feasible
to do so - clearly exemplified by the i486, AMD K5, Cyrix 6x86,
Motorola 68040, etc.
RISC instructions inherently perform more work per instruction (on
average), and are also normally highly encoded, so they enable smaller
overall size of the same program, and thus better use of limited cache
RISC implementations (e.g., x86 designs) decode
instructions into dynamically buffered micro-operations with
instruction encodings similar to traditional fixed microcode. Ordinary
static microcode is used as hardware assistance for complex multistep
operations such as auto-repeating instructions and for transcendental
functions in the floating point unit; it is also used for special
purpose instructions (such as CPUID) and internal control and
The simpler instructions in CISC architectures are also directly
executed in hardware in modern implementations.
RISC and VLIW processors are designed to execute every
instruction (as long as it is in the cache) in a single cycle. This is
very similar to the way CPUs with microcode execute one
microinstruction per cycle. VLIW processors have instructions that
behave similarly to very wide horizontal microcode, although typically
without such fine-grained control over the hardware as provided by
RISC instructions are sometimes similar to the narrow
Microcoding has been popular in application-specific processors such
as network processors.
Information technology portal
Address generation unit
Address generation unit (AGU)
Finite-state machine (FSM)
Floating-point unit (FPU)
IBM horizontally microcoded processors had multiple micro-orders and
register select fields that required decoding
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File Version: 20180312 on 3/12/2018]
Microcode Update Utility for Linux". Archived from the
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^ "ports/sysutils/devcpu/". Freebsd.org. 2008-09-23. Retrieved
^ "A microcode reliability update is available that improves the
reliability of systems that use
^ "BIOS Update required when Missing
Microcode message is seen during
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Look up microcode in Wiktionary, the free dictionary.
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Writable Instruction Set Computer
Capacitor Read-only Store
Transformer Read-only Store
A Brief History of Microprogramming
Intel processor microcode security update (fixes the issues when
32-bit virtual machines in PAE mode)
Microcode Updates, March 2013, by Ben Hawkes, archived
from the original on September 7, 2015
Hole seen in Intel's bug-busting feature, EE Times, 2002, by Alexander
Wolfe, archived from the original on March 9, 2003
Opteron Exposed: Reverse Engineering AMD K8
Microcode Updates, July
Universal Turing machine
Quantum Turing machine
Random access machine
Random access stored program machine
Artificial neural network
Neural processing unit (NPU)
Convolutional neural network
Register memory architecture
Adiabatic quantum computing
Linear optical quantum computing
Symmetric multiprocessing (SMP)
Asymmetric multiprocessing (AMP)
Power Architecture (PowerPC)
Memory dependence prediction
Simultaneous (SMT) (Hyper-threading)
Clustered Multi-Thread (CMT)
Instructions per second (IPS)
Instructions per clock (IPC)
Cycles per instruction (CPI)
Floating-point operations per second (FLOPS)
Transactions per second (TPS)
Synaptic Updates Per Second (SUPS)
Performance per watt
Orders of magnitude (computing)
Cache performance measurement and metric
Central processing unit
Central processing unit (CPU)
Vision processing unit (VPU)
Digital signal processor
Digital signal processor (DSP)
I/O processor/DMA controller
Physics processing unit
Physics processing unit (PPU)
Multi-chip module (MCM)
Chip stack multi-chip modules
System on a chip
System on a chip (SoC)
Multiprocessor system-on-chip (MPSoC)
Network on a chip (NoC)
Execution unit (EU)
Arithmetic logic unit
Arithmetic logic unit (ALU)
Address generation unit
Address generation unit (AGU)
Floating-point unit (FPU)
Load-store unit (LSU)
Unified Reservation Station
Sum addressed decoder (SAD)
Memory management unit
Memory management unit (MMU)
Input–output memory management unit
Input–output memory management unit (IOMMU)
Memory Controller (IMC)
Power Management Unit (PMU)
Translation lookaside buffer
Translation lookaside buffer (TLB)
Memory buffer register (MBR)
Three-dimensional integrated circuit
Mixed-signal integrated circuit
Power management integrated circuit
Emitter-coupled logic (ECL)
Transistor–transistor logic (TTL)
Dynamic frequency scaling
Dynamic voltage scaling
Non-executable memory (NX bit)
Memory Protection Extensions (
Intel Secure Key
Hardware restriction (firmware)
Software Guard Extensions (
Trusted Execution Technology
Trusted Platform Module
Trusted Platform Module (TPM)
Hardware security module
History of ge