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Microcode
Microcode
is "a technique that imposes an interpreter between the hardware and the architectural level of a computer".[1] As such, the microcode is a layer of hardware-level instructions that implement higher-level machine code instructions or internal state machine sequencing in many digital processing elements. Microcode
Microcode
is used in general-purpose central processing units, as well as in more specialized processors such as microcontrollers, digital signal processors, channel controllers, disk controllers, network interface controllers, network processors, graphics processing units, and in other hardware. Microcode
Microcode
typically resides in special high-speed memory and translates machine instructions, state machine data or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlying electronics so that instructions can be designed and altered more freely. It also facilitates the building of complex multi-step instructions, while reducing the complexity of computer circuits. Writing microcode is often called microprogramming and the microcode in a particular processor implementation is sometimes called a microprogram. More extensive microcoding allows small and simple microarchitectures to emulate more powerful architectures with wider word length, more execution units and so on, which is a relatively simple way to achieve software compatibility between different products in a processor family. Some hardware vendors, especially IBM, use the term microcode as a synonym for firmware. In that way, all code within a device is termed microcode regardless of it being microcode or machine code; for example, hard disk drives are said to have their microcode updated, though they typically contain both microcode and firmware.[2]

Contents

1 Overview 2 Justification

2.1 Benefits

3 History 4 Examples 5 Implementation

5.1 Horizontal microcode 5.2 Vertical microcode

6 Writable control store 7 Comparison to VLIW and RISC 8 See also 9 Notes 10 References 11 Further reading 12 External links

Overview[edit] When compared to normal application programs, the elements composing a microprogram exist on a lower conceptual level. To avoid confusion, each microprogram-related element is differentiated by the micro prefix: microinstruction, microassembler, microprogrammer, microarchitecture, etc. Engineers normally write the microcode during the design phase of a processor, storing it in a read-only memory (ROM) or programmable logic array (PLA)[3] structure, or in a combination of both.[4] However, machines also exist that have some or all microcode stored in SRAM or flash memory. This is traditionally denoted as writeable control store in the context of computers, which can be either read-only or read-write memory. In the latter case, the CPU initialization process loads microcode into the control store from another storage medium, with the possibility of altering the microcode to correct bugs in the instruction set, or to implement new machine instructions. Complex digital processors may also employ more than one (possibly microcode-based) control unit in order to delegate sub-tasks that must be performed essentially asynchronously in parallel. A high-level programmer, or even an assembly programmer, does not normally see or change microcode. Unlike machine code, which often retains some backward compatibility among different processors in a family, microcode only runs on the exact electronic circuitry for which it is designed, as it constitutes an inherent part of the particular processor design itself. Microprograms consist of series of microinstructions, which control the CPU at a very fundamental level of hardware circuitry. For example, a single typical horizontal microinstruction might specify the following operations:

Connect register 1 to the A side of the ALU Connect register 7 to the B side of the ALU Set the ALU to perform two's-complement addition Set the ALU's carry input to zero Store the result value in register 8 Update the condition codes from the ALU status flags (negative, zero, overflow, and carry) Microjump to microPC nnn for the next microinstruction

To simultaneously control all processor's features in one cycle, the microinstruction is often wider than 50 bits; e.g., 128 bits on a 360/85 with an emulator feature. Microprograms are carefully designed and optimized for the fastest possible execution, as a slow microprogram would result in a slow machine instruction and degraded performance for related application programs that use such instructions. Justification[edit] Microcode
Microcode
was originally developed as a simpler method of developing the control logic for a computer. Initially, CPU instruction sets were hardwired. Each step needed to fetch, decode, and execute the machine instructions (including any operand address calculations, reads, and writes) was controlled directly by combinational logic and rather minimal sequential state machine circuitry. While very efficient, the need for powerful instruction sets with multi-step addressing and complex operations (see below) made such hard-wired processors difficult to design and debug; highly encoded and varied-length instructions can contribute to this as well, especially when very irregular encodings are used. Microcode
Microcode
simplified the job by allowing much of the processor's behaviour and programming model to be defined via microprogram routines rather than by dedicated circuitry. Even late in the design process, microcode could easily be changed, whereas hard-wired CPU designs were very cumbersome to change. Thus, this greatly facilitated CPU design. From the 1940s to the late 1970s, a large portion of programming was done in assembly language; higher-level instructions mean greater programmer productivity, so an important advantage of microcode was the relative ease by which powerful machine instructions can be defined. The ultimate extension of this are "Directly Executable High Level Language" designs, in which each statement of a high-level language such as PL/I is entirely and directly executed by microcode, without compilation. The IBM
IBM
Future Systems project and Data General Fountainhead Processor are examples of this. During the 1970s, CPU speeds grew more quickly than memory speeds and numerous techniques such as memory block transfer, memory pre-fetch and multi-level caches were used to alleviate this. High-level machine instructions, made possible by microcode, helped further, as fewer more complex machine instructions require less memory bandwidth. For example, an operation on a character string can be done as a single machine instruction, thus avoiding multiple instruction fetches. Architectures with instruction sets implemented by complex microprograms included the IBM
IBM
System/360
System/360
and Digital Equipment Corporation VAX. The approach of increasingly complex microcode-implemented instruction sets was later called CISC. An alternate approach, used in many microprocessors, is to use PLAs or ROMs (instead of combinational logic) mainly for instruction decoding, and let a simple state machine (without much, or any, microcode) do most of the sequencing. The MOS Technology 6502
MOS Technology 6502
is an example of a microprocessor using a PLA for instruction decode and sequencing. The PLA is visible in photomicrographs of the chip,[5] and its operation can be seen in the transistor-level simulation. Microprogramming is still used in modern CPU designs. In some cases, after the microcode is debugged in simulation, logic functions are substituted for the control store.[citation needed] Logic functions are often faster and less expensive than the equivalent microprogram memory. Benefits[edit] A processor's microprograms operate on a more primitive, totally different, and much more hardware-oriented architecture than the assembly instructions visible to normal programmers. In coordination with the hardware, the microcode implements the programmer-visible architecture. The underlying hardware need not have a fixed relationship to the visible architecture. This makes it easier to implement a given instruction set architecture on a wide variety of underlying hardware micro-architectures. The IBM
IBM
System/360
System/360
has a 3 2-bit architecture with 16 general-purpose registers, but most of the System/360
System/360
implementations actually use hardware that implemented a much simpler underlying microarchitecture; for example, the System/360
System/360
Model 30 has 8-bit data paths to the arithmetic logic unit (ALU) and main memory and implemented the general-purpose registers in a special unit of higher-speed core memory, and the System/360
System/360
Model 40 has 8-bit data paths to the ALU and 16-bit data paths to main memory and also implemented the general-purpose registers in a special unit of higher-speed core memory. The Model 50 has full 32-bit
32-bit
data paths and implements the general-purpose registers in a special unit of higher-speed core memory.[6] The Model 65 through the Model 195 have larger data paths and implement the general-purpose registers in faster transistor circuits.[citation needed] In this way, microprogramming enabled IBM to design many System/360
System/360
models with substantially different hardware and spanning a wide range of cost and performance, while making them all architecturally compatible. This dramatically reduces the number of unique system software programs that must be written for each model. A similar approach was used by Digital Equipment Corporation
Digital Equipment Corporation
(DEC) in their VAX
VAX
family of computers. As a result, different VAX
VAX
processors use different microarchitectures, yet the programmer-visible architecture does not change. Microprogramming also reduces the cost of field changes to correct defects (bugs) in the processor; a bug can often be fixed by replacing a portion of the microprogram rather than by changes being made to hardware logic and wiring. History[edit] In 1947, the design of the MIT Whirlwind introduced the concept of a control store as a way to simplify computer design and move beyond ad hoc methods. The control store is a diode matrix: a two-dimensional lattice, where one dimension accepts "control time pulses" from the CPU's internal clock, and the other connects to control signals on gates and other circuits. A "pulse distributor" takes the pulses generated by the CPU clock and breaks them up into eight separate time pulses, each of which activates a different row of the lattice. When the row is activated, it activates the control signals connected to it.[7] Described another way, the signals transmitted by the control store are being played much like a player piano roll. That is, they are controlled by a sequence of very wide words constructed of bits, and they are "played" sequentially. In a control store, however, the "song" is short and repeated continuously. In 1951, Maurice Wilkes
Maurice Wilkes
enhanced this concept by adding conditional execution, a concept akin to a conditional in computer software. His initial implementation consisted of a pair of matrices: the first one generated signals in the manner of the Whirlwind control store, while the second matrix selected which row of signals (the microprogram instruction word, so to speak) to invoke on the next cycle. Conditionals were implemented by providing a way that a single line in the control store could choose from alternatives in the second matrix. This made the control signals conditional on the detected internal signal. Wilkes coined the term microprogramming to describe this feature and distinguish it from a simple control store. Examples[edit]

An American Megatrends
American Megatrends
BIOS showing a " Intel
Intel
CPU uCode Loading Error" after a failed attempt to upload microcode patches into the CPU.

In common with many other complex mechanical devices, Charles Babbage's analytical engine uses banks of cams to control each operation. That is, it has a read-only control store. As such, it deserves to be recognised as the first microprogrammed computer to be designed, although it had not been implemented in hardware until 2002.[8] The EMIDEC 1100[9] reputedly uses a hard-wired control store consisting of wires threaded through ferrite cores, known as "the laces". Most models of the IBM
IBM
System/360
System/360
series are microprogrammed:

The Model 25 is unique among System/360
System/360
models in using the top 16 K bytes of core storage to hold the control storage for the microprogram. The 2025 uses a 16-bit microarchitecture with seven control words (or microinstructions). At power up, or full system reset, the microcode is loaded from the card reader. The IBM
IBM
1410 emulation for this model is loaded this way. The Model 30, the slowest model in the line, uses an 8-bit microarchitecture with only a few hardware registers; everything that the programmer saw is emulated by the microprogram. The microcode for this model is also held on special punched cards, which are stored inside the machine in a dedicated reader per card, called "CROS" units (Capacitor Read-Only Storage). A second CROS reader is installed for machines ordered with 1620 emulation. The Model 40 uses 56-bit control words. The 2040 box implements both the System/360
System/360
main processor and the multiplex channel (the I/O processor). This model uses "TROS" dedicated readers similar to "CROS" units, but with an inductive pickup (Transformer Read-only Store). The Model 50 has two internal datapaths which operated in parallel: a 32-bit
32-bit
datapath used for arithmetic operations, and an 8-bit data path used in some logical operations. The control store uses 90-bit microinstructions. The Model 85 has separate instruction fetch (I-unit) and execution (E-unit) to provide high performance. The I-unit is hardware controlled. The E-unit is microprogrammed; the control words are 108 bits wide on a basic 360/85 and wider if an emulator feature is installed.

The NCR 315 is microprogrammed with hand wired ferrite cores (a ROM) pulsed by a sequencer with conditional execution. Wires routed through the cores are enabled for various data and logic elements in the processor. The Digital Equipment Corporation
Digital Equipment Corporation
PDP-11
PDP-11
processors, with the exception of the PDP-11/20, are microprogrammed.[10] Most Data General
Data General
Eclipse minicomputers are microprogrammed. The task of writing microcode for the Eclipse MV/8000 is detailed in the Pulitzer Prize-winning book titled The Soul of a New Machine. Many systems from Burroughs are microprogrammed:

The B700 "microprocessor" execute application-level opcodes using sequences of 16-bit microinstructions stored in main memory; each of these is either a register-load operation or mapped to a single 56-bit "nanocode" instruction stored in read-only memory. This allows comparatively simple hardware to act either as a mainframe peripheral controller or to be packaged as a standalone computer. The B1700 is implemented with radically different hardware including bit-addressable main memory but has a similar multi-layer organisation. The operating system preloads the interpreter for whatever language is required. These interpreters present different virtual machines for COBOL, Fortran, etc.

Microdata produced computers in which the microcode is accessible to the user; this allows the creation of custom assembler level instructions. Microdata's Reality operating system design makes extensive use of this capability. The Xerox Alto workstation used a microcoded design but, unlike many computers, the microcode engine is not hidden from the programmer in a layered design. Applications take advantage of this to accelerate performance. The Nintendo 64's Reality Coprocessor
Reality Coprocessor
(RCP), which serves as the console's graphics processing unit and audio processor, utilizes microcode; it is possible to implement new effects or tweak the processor to achieve the desired output. Some notable examples of custom RCP microcode include the high-resolution graphics, particle engines, and unlimited draw distances found in Factor 5's Indiana Jones and the Infernal Machine, Star Wars: Rogue Squadron, and Star Wars: Battle for Naboo;[11][12] and the full motion video playback found in Angel Studios' Resident Evil 2.[13]

Further information on Nintendo 64
Nintendo 64
microcode: Nintendo 64
Nintendo 64
programming characteristics and Nintendo 64
Nintendo 64
Game Pak

The VU0 and VU1 vector units in the Sony
Sony
PlayStation 2
PlayStation 2
are microprogrammable; in fact, VU1 is only accessible via microcode for the first several generations of the SDK. The MicroCore Labs MCL86 and MCL51 are examples of highly encoded "vertical" microsequencer implementations of the Intel
Intel
8086/8088 and the Intel
Intel
8051.

Implementation[edit] Each microinstruction in a microprogram provides the bits that control the functional elements that internally compose a CPU. The advantage over a hard-wired CPU is that internal CPU control becomes a specialized form of a computer program. Microcode
Microcode
thus transforms a complex electronic design challenge (the control of a CPU) into a less complex programming challenge. To take advantage of this, a CPU is divided into several parts:

A microsequencer picks the next word of the control store. A sequencer is mostly a counter, but usually also has some way to jump to a different part of the control store depending on some data, usually data from the instruction register and always some part of the control store. The simplest sequencer is just a register loaded from a few bits of the control store. A register set is a fast memory containing the data of the central processing unit. It may include the program counter, stack pointer, and other numbers that are not easily accessible to the application programmer. Often the register set is a triple-ported register file; that is, two registers can be read, and a third written at the same time. An arithmetic and logic unit performs calculations, usually addition, logical negation, a right shift, and logical AND. It often performs other functions, as well.

There may also be a memory address register and a memory data register, used to access the main computer storage. Together, these elements form an "execution unit". Most modern CPUs have several execution units. Even simple computers usually have one unit to read and write memory, and another to execute user code. These elements could often be brought together as a single chip. This chip comes in a fixed width that would form a "slice" through the execution unit. These are known as "bit slice" chips. The AMD Am2900
AMD Am2900
family is one of the best known examples of bit slice elements. The parts of the execution units and the execution units themselves are interconnected by a bundle of wires called a bus. Programmers develop microprograms, using basic software tools. A microassembler allows a programmer to define the table of bits symbolically. Because of its close relationship to the underlying architecture, "microcode has several properties that make it difficult to generate using a compiler."[1] A simulator program is intended to execute the bits in the same way as the electronics, and allows much more freedom to debug the microprogram. After the microprogram is finalized, and extensively tested, it is sometimes used as the input to a computer program that constructs logic to produce the same data.[citation needed] This program is similar to those used to optimize a programmable logic array. Even without fully optimal logic, heuristically optimized logic can vastly reduce the number of transistors from the number required for a ROM control store. This reduces the cost of producing, and the electricity consumed by, a CPU. Microcode
Microcode
can be characterized as horizontal or vertical, referring primarily to whether each microinstruction controls CPU elements with little or no decoding (horizontal microcode)[a] or requires extensive decoding by combinatorial logic before doing so (vertical microcode). Consequently, each horizontal microinstruction is wider (contains more bits) and occupies more storage space than a vertical microinstruction. Horizontal microcode[edit] "Horizontal microcode has several discrete micro-operations that are combined in a single microinstruction for simultaneous operation."[1] Horizontal microcode is typically contained in a fairly wide control store; it is not uncommon for each word to be 108 bits or more. On each tick of a sequencer clock a microcode word is read, decoded, and used to control the functional elements that make up the CPU. In a typical implementation a horizontal microprogram word comprises fairly tightly defined groups of bits. For example, one simple arrangement might be:

Register source A Register source B Destination register Arithmetic and logic unit
Arithmetic and logic unit
operation Type of jump Jump address

For this type of micromachine to implement a JUMP instruction with the address following the opcode, the microcode might require two clock ticks. The engineer designing it would write microassembler source code looking something like this:

# Any line starting with a number-sign is a comment # This is just a label, the ordinary way assemblers symbolically represent a # memory address. InstructionJUMP: # To prepare for the next instruction, the instruction-decode microcode has already # moved the program counter to the memory address register. This instruction fetches # the target address of the jump instruction from the memory word following the # jump opcode, by copying from the memory data register to the memory address register. # This gives the memory system two clock ticks to fetch the next

# instruction to the memory data register for use by the instruction decode. # The sequencer instruction "next" means just add 1 to the control word address. MDR, NONE, MAR, COPY, NEXT, NONE # This places the address of the next instruction into the PC. # This gives the memory system a clock tick to finish the fetch started on the # previous microinstruction. # The sequencer instruction is to jump to the start of the instruction decode. MAR, 1, PC, ADD, JMP, InstructionDecode # The instruction decode is not shown, because it is usually a mess, very particular # to the exact processor being emulated. Even this example is simplified. # Many CPUs have several ways to calculate the address, rather than just fetching # it from the word following the op-code. Therefore, rather than just one # jump instruction, those CPUs have a family of related jump instructions.

For each tick it is common to find that only some portions of the CPU are used, with the remaining groups of bits in the microinstruction being no-ops. With careful design of hardware and microcode, this property can be exploited to parallelise operations that use different areas of the CPU; for example, in the case above, the ALU is not required during the first tick, so it could potentially be used to complete an earlier arithmetic instruction. Vertical microcode[edit] In vertical microcode, each microinstruction is significantly encoded – that is, the bit fields generally pass through intermediate combinatory logic that, in turn, generates the actual control and sequencing signals for internal CPU elements (ALU, registers, etc.). This is in contrast with horizontal microcode, in which the bit fields themselves either directly produce the control and sequencing signals or are only minimally encoded. Consequently, vertical microcode requires smaller instruction lengths and less storage, but requires more time to decode, resulting in a slower CPU clock.[14] Some vertical microcode is just the assembly language of a simple conventional computer that is emulating a more complex computer. Some processors, such as DEC Alpha
DEC Alpha
processors and the CMOS microprocessors on later IBM
IBM
System/390
System/390
mainframes and z/Architecture mainframes, have PALcode (the term used on Alpha processors) or millicode (the term used on IBM
IBM
mainframe microprocessors). This is a form of machine code, with access to special registers and other hardware resources not available to regular machine code, used to implement some instructions and other functions, such as page table walks on Alpha processors.[15][16][17] Another form of vertical microcode has two fields:

Field select Field value

The field select selects which part of the CPU will be controlled by this word of the control store. The field value actually controls that part of the CPU. With this type of microcode, a designer explicitly chooses to make a slower CPU to save money by reducing the unused bits in the control store; however, the reduced complexity may increase the CPU's clock frequency, which lessens the effect of an increased number of cycles per instruction. As transistors became cheaper, horizontal microcode came to dominate the design of CPUs using microcode, with vertical microcode being used less often. When both vertical and horizontal microcode are used, the horizontal microcode may be referred to as nanocode or picocode.[18] Writable control store[edit] Main article: Writable control store A few computers were built using "writable microcode". In this design, rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a writable control store or WCS. Such a computer is sometimes called a writable instruction set computer or WISC.[19] Many experimental prototype computers use writable control stores; there are also commercial machines that use writable microcode, such as the Burroughs Small Systems, early Xerox workstations, the DEC VAX 8800 ("Nautilus") family, the Symbolics
Symbolics
L- and G-machines, a number of IBM
IBM
System/360
System/360
and System/370
System/370
implementations, some DEC PDP-10 machines,[20] and the Data General
Data General
Eclipse MV/8000.[21] Many more machines offer user-programmable writable control stores as an option, including the HP 2100, DEC PDP-11/60 and Varian Data Machines V-70 series minicomputers. The IBM
IBM
System/370
System/370
includes a facility called Initial-Microprogram Load (IML or IMPL)[22] that can be invoked from the console, as part of power-on reset (POR) or from another processor in a tightly coupled multiprocessor complex. Some commercial machines, for example IBM
IBM
360/85,[23][24] have both a read-only storage and a writable control store for microcode. WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs can provide. User-programmable WCS allows the user to optimize the machine for specific purposes. Starting with the Pentium Pro
Pentium Pro
in 1995, several Intel
Intel
x86 CPUs have writable microcode.[25][26] This, for example, has allowed bugs in the Intel
Intel
Core 2 and Intel
Intel
Xeon
Xeon
microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced. A second prominent example is the set of microcode patches that Intel
Intel
offered for improving the capabilities of processor architectures of up to nearly 10 years in age in the progress of counter fighting the serious Spectre and Meltdown security dangers as went really public in start of 2018.[27][28] A microcode update can be installed by Linux,[29] FreeBSD,[30] Microsoft Windows,[31] or the motherboard BIOS.[32] Comparison to VLIW and RISC[edit] The design trend toward heavily microcoded processors with complex instructions began in the early 1960s and continued until roughly the mid-1980s. At that point the RISC
RISC
design philosophy started becoming more prominent. A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction. Some CISC processors include instructions that can take a very long time to execute. Such variations interfere with both interrupt latency and, what is far more important in modern systems, pipelining. When designing a new processor, a hardwired control RISC
RISC
has the following advantages over microcoded CISC:

Programming has largely moved away from assembly level, so it's no longer worthwhile to provide complex instructions for productivity reasons. Simpler instruction sets allow direct execution by hardware, avoiding the performance penalty of microcoded execution. Analysis shows complex instructions are rarely used, hence the machine resources devoted to them are largely wasted. The machine resources devoted to rarely used complex instructions are better used for expediting performance of simpler, commonly used instructions. Complex microcoded instructions may require many clock cycles that vary, and are difficult to pipeline for increased performance.

There are counterpoints as well:

The complex instructions in heavily microcoded implementations may not take much extra machine resources, except for microcode space. For instance, the same ALU is often used to calculate an effective address as well as computing the result from the actual operands (e.g., the original Z80, 8086, and others). The simpler non- RISC
RISC
instructions (i.e., involving direct memory operands) are frequently used by modern compilers. Even immediate to stack (i.e., memory result) arithmetic operations are commonly employed. Although such memory operations, often with varying length encodings, are more difficult to pipeline, it is still fully feasible to do so - clearly exemplified by the i486, AMD K5, Cyrix 6x86, Motorola 68040, etc. Non- RISC
RISC
instructions inherently perform more work per instruction (on average), and are also normally highly encoded, so they enable smaller overall size of the same program, and thus better use of limited cache memories. Modern CISC/ RISC
RISC
implementations (e.g., x86 designs) decode instructions into dynamically buffered micro-operations with instruction encodings similar to traditional fixed microcode. Ordinary static microcode is used as hardware assistance for complex multistep operations such as auto-repeating instructions and for transcendental functions in the floating point unit; it is also used for special purpose instructions (such as CPUID) and internal control and configuration purposes. The simpler instructions in CISC architectures are also directly executed in hardware in modern implementations.

Many RISC
RISC
and VLIW processors are designed to execute every instruction (as long as it is in the cache) in a single cycle. This is very similar to the way CPUs with microcode execute one microinstruction per cycle. VLIW processors have instructions that behave similarly to very wide horizontal microcode, although typically without such fine-grained control over the hardware as provided by microcode. RISC
RISC
instructions are sometimes similar to the narrow vertical microcode. Microcoding has been popular in application-specific processors such as network processors. See also[edit]

Electronics
Electronics
portal Information technology portal

Address generation unit
Address generation unit
(AGU) CPU design Finite-state machine
Finite-state machine
(FSM) Firmware Floating-point unit
Floating-point unit
(FPU) Instruction pipeline MikroSim Millicode Superscalar

Notes[edit]

^ IBM
IBM
horizontally microcoded processors had multiple micro-orders and register select fields that required decoding

References[edit]

^ a b c Kent, Allen; Williams, James G. (April 5, 1993). Encyclopedia of Computer Science and Technology: Volume 28 - Supplement 13. New York: Marcel Dekker, Inc. ISBN 0-8247-2281-7. Retrieved Jan 17, 2016.  ^ " IBM
IBM
pSeries Servers - Microcode
Microcode
Update for Ultrastar 73LZX (US73) 18/36 GB". ibm.com. Retrieved January 22, 2015.  ^ Manning, B.M.; Mitby, J.S; Nicholson, J.O. (November 1979). "Microprogrammed Processor Having PLA Control Store". IBM
IBM
Technical Disclosure Bulletin. 22 (6).  ^ Often denoted a ROM/PLA control store in the context of usage in a CPU; "J-11: DEC's fourth and last PDP-11
PDP-11
microprocessor design ... features ... ROM/PLA control store".  ^ "6502 Images". Retrieved January 22, 2015.  ^ IBM
IBM
System/360
System/360
Model 50 Functional Characteristics (PDF). IBM. 1967. p. 7. Retrieved September 20, 2011.  ^ Everett, R.R. & Swain, F.E. (1947). "Whirlwind I Computer Block Diagrams" (PDF). Report R-127. MIT Servomechanisms Laboratory. Archived from the original (PDF) on June 17, 2012. Retrieved June 21, 2006.  ^ "The Babbage Engine". Retrieved 11 December 2015.  ^ " EMIDEC 1100
EMIDEC 1100
computer". Emidec.org.uk. Retrieved April 26, 2010.  ^ Daniel P. Siewiorek, C. Gordon Bell, Allen Newell (1982). Computer Structures: Principles and Examples. New York, NY: McGraw-Hill
McGraw-Hill
Book Company. ISBN 0-07-057302-6. CS1 maint: Multiple names: authors list (link) ^ "Interview: Battling the N64 (Naboo)". IGN64. November 10, 2000. Retrieved March 27, 2008.  ^ "Indiana Jones and the Infernal Machine". IGN. December 12, 2000. Retrieved September 24, 2013.  ^ Meynink, Todd (July 28, 2000). "Postmortem: Angel Studios' Resident Evil 2 (N64 Version)". Gamasutra. United Business Media
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LLC. Retrieved October 18, 2010.  ^ Neal Harman; Andy Gimblett (2009-10-12). "CS-323: High Performance Microprocessors – Chapter 1. Microprogramming". mat.uson.mx. Retrieved 2015-08-08.  ^ " PALcode for Alpha Microprocessors System Design Guide" (PDF). Digital Equipment Corporation. May 1996. Retrieved November 7, 2013.  ^ Robert Vaupel. High Availability and Scalability of Mainframe Environments using System z and z/OS as example. ISBN 978-3-7315-0022-3.  ^ Rogers, Bob (Sep–Oct 2012). "The What and Why of zEnterprise Millicode". IBM
IBM
Systems Magazine.  ^ Spruth, Wilhelm (Dec 2012). The Design of a Microprocessor. Springer Science & Business Media. p. 31. ISBN 978-3-642-74916-2. Retrieved Jan 18, 2015.  ^ "Writable instruction set, stack oriented computers: The WISC Concept" article by Philip Koopman Jr. 1987 ^ Eric Smith, 3 September 2002, "Re: What was the size of Microcode
Microcode
in various machines" ^ Mark Smotherman. "CPSC 330 / The Soul of a New Machine". 4096 x 75-bit SRAM writeable control store: 7 4-bit
4-bit
microinstruction with 1 parity bit (18 fields)  ^ IBM
IBM
System/370
System/370
Principles of Operation (PDF). Fourth Edition. IBM. September 1974. pp. 98, 245. GA22-7000-4.  ^ IBM
IBM
System/360
System/360
Model 85 Functional Characteristics (PDF). SECOND EDITION. IBM. June 1968. A22-6916-1.  ^ IBM
IBM
System/360
System/360
Special
Special
Feature Description 709/7090/7094 Compatibility Feature for IBM
IBM
System/360
System/360
Model 85. First Edition. IBM. March 1969. GA27-2733-0.  ^ Stiller, Andreas; Paul, Matthias (1996-05-12). "Prozessorgeflüster". c't – magazin für computertechnik. Trends & News (in German). Heise Verlag. Archived from the original on 2017-08-28. Retrieved 2017-08-28.  ^ "Intel(R) 64 and IA-32 Architectures Software Developer’s Manual", Volume 3A: System Programming Guide, Part 1, chapter 9.11: "Microcode update facilities", December 2009. ^ Intel
Intel
Patches All Recent CPUs, Promises Hardware Fixes For Upcoming 8th Gen Chips by Paul Alcorn on March 15, 2018 ^ Linux* Processor Microcode
Microcode
Data File
File
Version: 20180312 on 3/12/2018] ^ " Intel
Intel
Microcode
Microcode
Update Utility for Linux". Archived from the original on 2012-02-26.  ^ "ports/sysutils/devcpu/". Freebsd.org. 2008-09-23. Retrieved 2010-04-26.  ^ "A microcode reliability update is available that improves the reliability of systems that use Intel
Intel
processors" ^ "BIOS Update required when Missing Microcode
Microcode
message is seen during POST"

Further reading[edit]

Smith, Richard E. (1988). "A Historical Overview of Computer Architecture". Annals of the History of Computing. 10 (4): 277–303. doi:10.1109/MAHC.1988.10039. Retrieved June 21, 2006.  Smotherman, Mark (2005). "A Brief History of Microprogramming". Retrieved July 30, 2006.  Wilkes, M.V. (1986). "The Genesis of Microprogramming". Annals of the History of Computing. 8 (2): 116–126. doi:10.1109/MAHC.1986.10035. Retrieved August 7, 2006.  Wilkes, M.V., and Stringer, J. B. (April 1953). "Microprogramming and the Design of the Control Circuits in an Electronic Digital Computer". Proc. Cambridge Phil. Soc. 49 (pt. 2): 230–238. doi:10.1017/S0305004100028322. Retrieved August 23, 2006. CS1 maint: Multiple names: authors list (link) Husson, S.S (1970). Microprogramming Principles and Practices. Prentice-Hall. ISBN 0-13-581454-5.  Tucker, S. G., "Microprogram control for SYSTEM/360" IBM
IBM
Systems Journal, Volume 6, Number 4, pp. 222–241 (1967)

External links[edit]

Look up microcode in Wiktionary, the free dictionary.

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Writable Instruction Set Computer Capacitor Read-only Store Transformer Read-only Store A Brief History of Microprogramming Intel
Intel
processor microcode security update (fixes the issues when running 32-bit
32-bit
virtual machines in PAE mode) Notes on Intel
Intel
Microcode
Microcode
Updates, March 2013, by Ben Hawkes, archived from the original on September 7, 2015 Hole seen in Intel's bug-busting feature, EE Times, 2002, by Alexander Wolfe, archived from the original on March 9, 2003 Opteron Exposed: Reverse Engineering AMD K8 Microcode
Microcode
Updates, July 26, 2004

v t e

CPU technologies

Architecture

Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network

Machine learning Deep learning Neural processing unit (NPU)

Convolutional neural network Load/store architecture Register memory architecture Endianness FIFO Zero-copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing
Symmetric multiprocessing
(SMP) Asymmetric multiprocessing
Asymmetric multiprocessing
(AMP) Cache hierarchy Memory hierarchy

ISA types

ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison

ISAs

x86 z/Architecture ARM MIPS Power Architecture
Power Architecture
(PowerPC) SPARC Mill Itanium
Itanium
(IA-64) Alpha Prism SuperH V850 Clipper VAX Unicore PA-RISC MicroBlaze RISC-V

Word size

1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable

Execution

Instruction pipelining

Bubble Operand forwarding

Out-of-order execution

Register renaming

Speculative execution

Branch predictor Memory dependence prediction

Hazards

Parallel level

Bit

Bit-serial Word

Instruction Pipelining

Scalar Superscalar

Task

Thread Process

Data

Vector

Memory

Multithreading

Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout

Flynn's taxonomy

SISD SIMD
SIMD
(SWAR) SIMT MISD MIMD

SPMD

Addressing mode

CPU performance

Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric

Core count

Single-core processor Multi-core processor Manycore processor

Types

Central processing unit
Central processing unit
(CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor
Digital signal processor
(DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit
Physics processing unit
(PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module
Multi-chip module
(MCM) Chip stack multi-chip modules System on a chip
System on a chip
(SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip
System-on-Chip
(PSoC) Network on a chip (NoC)

Components

Execution unit (EU) Arithmetic logic unit
Arithmetic logic unit
(ALU) Address generation unit
Address generation unit
(AGU) Floating-point unit
Floating-point unit
(FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit
Memory management unit
(MMU) Input–output memory management unit
Input–output memory management unit
(IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer
Translation lookaside buffer
(TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode
Microcode
ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate

Combinational logic Sequential logic Emitter-coupled logic
Emitter-coupled logic
(ECL) Transistor–transistor logic
Transistor–transistor logic
(TTL) Glue logic

Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor

Power management

APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security

Non-executable memory (NX bit) Memory Protection Extensions ( Intel
Intel
MPX) Intel
Intel
Secure Key Hardware restriction (firmware) Software Guard Extensions ( Intel
Intel
SGX) Trusted Execution Technology Trusted Platform Module
Trusted Platform Module
(TPM) Secure cryptoprocessor Hardware security module Hengzhi chip

Related

History of ge

.