The Info List - Memory Controller

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The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an integral part of a microprocessor; in the latter case, it is usually called an integrated memory controller (IMC). A memory controller is sometimes also called a memory chip controller (MCC)[1] or a memory controller unit (MCU).[2]


1 History 2 Purpose 3 Security 4 Variants

4.1 Double data rate
Double data rate
memory 4.2 Dual-channel memory 4.3 Fully buffered memory 4.4 Flash memory
Flash memory

5 See also 6 References 7 External links

History[edit] Most modern desktop or workstation microprocessors use an integrated memory controller (IMC), including microprocessors from Intel, AMD, and those built around the ARM architecture. Prior to K8 (circa 2003), AMD
microprocessors had a memory controller implemented on their motherboard's northbridge. In K8 and later, AMD employed an integrated memory controller.[3] Likewise, until Nehalem (circa 2008), Intel
microprocessors used memory controllers implemented on the motherboard's northbridge. Nehalem and later switched to an integrated memory controller.[4] Other examples of microprocessors that use integrated memory controllers include IBM's POWER5, and Sun Microsystems's UltraSPARC T1. While an integrated memory controller has the potential to increase the system's performance, such as by reducing memory latency, it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When DDR2 SDRAM
was introduced, AMD
released new Athlon 64 CPUs. These new models, with a DDR2 controller, use a different physical socket (known as Socket AM2), so that they will only fit in motherboards designed for the new type of RAM. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge. Some microprocessors in the 1990s, such as the DEC Alpha 21066
Alpha 21066
and HP PA-7300LC, had integrated memory controllers; however, rather than for performance gains, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller. Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM
POWER8, which uses external Centaur chips that are mounted onto DIMM
modules and act as memory buffers, L4 cache
L4 cache
chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.[5] Purpose[edit] Memory controllers contain the logic necessary to read and write to DRAM, and to "refresh" the DRAM. Without constant refreshes, DRAM will lose the data written to it as the capacitors leak their charge within a fraction of a second (not more than 64 milliseconds according to JEDEC
standards). Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation. Bus width is the number of parallel lines available to communicate with the memory cell. Memory controllers' bus widths range from 8-bit in earlier systems, to 5 12-bit in more complicated systems and video cards (typically implemented as four 64-bit simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a 12 8-bit memory device). Some memory controllers, such as the one integrated into PowerQUICC
II processors, can be connected to different kinds of devices at the same time, including SDRAM, SRAM, ROM, and memory-mapped I/O; each kind of these devices requires a slightly different control bus, while the memory controller presents a common system bus / front-side bus to the processor. Some memory controllers, such as the one integrated into PowerQUICC
II processors, include error detection and correction hardware.[6] Security[edit] A few experimental memory controllers (mostly aimed at the server market where data protection is legally required) contain a second level of address translation, in addition to the first level of address translation performed by the CPU's memory management unit.[7] Memory controllers integrated into certain Intel
Core processors also provide memory scrambling as a feature that turns user data written to the main memory into pseudo-random patterns.[8][9] Memory Scrambling (in Cryptographic Theory) is supposed to prevent forensic and reverse-engineering analysis based on DRAM data remanence by effectively rendering various types of cold boot attacks ineffective. In current practice this has not been achieved. However Memory Scrambling has only been designed to address DRAM-related electrical problems. The late 2010s Memory Scrambling Standards do not fix or prevent security issues or problems. The 2010s Memory Scrambling standards are not cryptographically secure, or necessarily open soured or open to public revision or anlysis.[10] ASUS and Intel
have their own memory scrambling standards. Currently ASUS motherboards have allowed the user to chose which memory scrambling standards to use [ASUS or Intel] or weather to turn the feature off entirely. Variants[edit] Double data rate
Double data rate
memory[edit] Double data rate
Double data rate
(DDR) memory controllers are used to drive DDR SDRAM, where data is transferred on both rising and falling edges of the system's memory clock. DDR memory controllers are significantly more complicated when compared to single data rate controllers[citation needed], but they allow for twice the data to be transferred without increasing the memory cell's clock rate or bus width. Dual-channel memory[edit] Dual Channel
Dual Channel
memory controllers are memory controllers where the DRAM devices are separated on to two different buses to allow two memory controllers to access them in parallel. This doubles the theoretical amount of bandwidth of the bus. In theory, more channels can be built (a channel for every DRAM cell would be the ideal solution), but due to wire count, line capacitance, and the need for parallel access lines to have identical lengths, more channels are very difficult to add. Fully buffered memory[edit] Main article: Fully Buffered DIMM Fully buffered memory systems place a memory buffer device on every memory module (called an FB- DIMM
when Fully Buffered RAM is used), which unlike traditional memory controller devices, use a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB- DIMM
controller, and back to a parallel form in the memory controller on the motherboard. In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy. Flash memory
Flash memory
controller[edit] Main article: Flash memory
Flash memory
controller Many flash memory devices, such as USB memory sticks, include a flash memory controller on chip. Flash memory
Flash memory
is inherently slower to access than RAM and often becomes unusable after a few million write cycles, which generally makes it unsuitable for RAM applications. See also[edit]

Memory scrubbing


^ Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU." ^ "Maximizing Performance and Scalability with IBM
WebSphere". google.com. Retrieved 6 February 2015.  ^ Vries, Hans de. "Chip Architect: AMD's Next Generation Micro Processor's Architecture". www.chip-architect.com. Retrieved 2018-03-17.  ^ Torres, Gabriel (2008-08-26). "Inside Intel
Nehalem Microarchitecture". Hardware Secrets. p. 2. Retrieved 7 September 2017.  ^ Prickett Morgan, Timothy (2016-10-17). " IBM
Brings DDR4 Memory To Bear On Power Systems" (HTML). IT Jungle. p. 1. Retrieved 2017-09-07.  ^ "Memory Controller" ^ This is a security feature in that it allows the Operating System to provide better protection separate from using a bit to deny arbitrary code execution in (System and/or User) RAM memory areas. John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, et al. "Impulse: Building a Smarter Memory Controller". ^ "2nd Generation Intel
Core Processor Family Desktop, Intel
Pentium Processor Family Desktop, and Intel
Celeron Processor Family Desktop" (PDF). June 2013. p. 23. Retrieved 2015-11-03.  ^ "2nd Generation Intel
Core Processor Family Mobile and Intel
Celeron Processor Family Mobile" (PDF). September 2012. p. 24. Retrieved 2015-11-03.  ^ Igor Skochinsky (2014-03-12). "Secret of Intel
Management Engine". SlideShare. pp. 26–29. Retrieved 2014-07-13. 

External links[edit]

Infineon/Kingston (a memory vendor) Dual Channel
Dual Channel
DDR Memory Whitepaper – explains dual channel memory controllers, and how to use them

v t e

CPU technologies


Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network

Machine learning Deep learning Neural processing unit (NPU)

Convolutional neural network Load/store architecture Register memory architecture Endianness FIFO Zero-copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing
Symmetric multiprocessing
(SMP) Asymmetric multiprocessing
Asymmetric multiprocessing
(AMP) Cache hierarchy Memory hierarchy

ISA types



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Power Architecture
(PowerPC) SPARC Mill Itanium
(IA-64) Alpha Prism SuperH V850 Clipper VAX Unicore PA-RISC MicroBlaze RISC-V

Word size

1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable


Instruction pipelining

Bubble Operand forwarding

Out-of-order execution

Register renaming

Speculative execution

Branch predictor Memory dependence prediction


Parallel level


Bit-serial Word

Instruction Pipelining

Scalar Superscalar


Thread Process





Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout

Flynn's taxonomy



Addressing mode

CPU performance

Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric

Core count

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Digital signal processor
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Multi-chip module
(MCM) Chip stack multi-chip modules System on a chip
System on a chip
(SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip
(PSoC) Network on a chip (NoC)


Execution unit (EU) Arithmetic logic unit
Arithmetic logic unit
(ALU) Address generation unit
Address generation unit
(AGU) Floating-point unit
Floating-point unit
(FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit
Memory management unit
(MMU) Input–output memory management unit
Input–output memory management unit
(IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer
Translation lookaside buffer
(TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode
ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate

Combinational logic Sequential logic Emitter-coupled logic
Emitter-coupled logic
(ECL) Transistor–transistor logic
Transistor–transistor logic
(TTL) Glue logic

Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor

Power management

APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security

Non-executable memory (NX bit) Memory Protection Extensions ( Intel
MPX) Intel
Secure Key Hardware restriction (firmware) Software Guard Extensions ( Intel
SGX) Trusted Execution Technology Trusted Platform Module
Trusted Platform Module
(TPM) Secure cryptoprocessor Hardware security module Hengzhi chip


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