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The Blackfin
Blackfin
is a family of 16- or 32-bit
32-bit
microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit Multiply–accumulates (MACs), accompanied on-chip by a small microcontroller.[1] It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.[2][3]

Contents

1 Architecture details 2 Architecture features

2.1 Core features 2.2 Memory and DMA 2.3 Microcontroller
Microcontroller
features 2.4 Media-processing features

3 Peripherals 4 Development tools 5 Supported operating systems, RTOSs and kernels 6 See also 7 References 8 External links

Architecture details[edit] Blackfin
Blackfin
processors use a 32-bit
32-bit
RISC
RISC
microcontroller programming model on a SIMD
SIMD
architecture, which was co-developed by Intel
Intel
and Analog Devices, as MSA (Micro Signal Architecture). The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001. It incorporates aspects of ADI's older SHARC architecture and Intel's XScale
XScale
architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC
RISC
architecture designs. The Blackfin
Blackfin
architecture encompasses various CPU models, each targeting particular applications.[4] Architecture features[edit]

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Core features[edit]

mounted Blackfin
Blackfin
BF535

What is regarded as the Blackfin
Blackfin
"core" is contextually dependent. For some applications, the DSP features are central. Blackfin
Blackfin
has two 16-bit hardware MACs, two 40-bit ALUs, and a 40-bit barrel shifter. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler or programmer. Two nested zero-overhead loops and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions. Other applications utilize the RISC
RISC
features, which include memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals. The ISA is designed for a high level of expressiveness, allowing the assembly programmer (or compiler) to optimize an algorithm for the hardware features present. Memory and DMA[edit] The Blackfin
Blackfin
uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers reside in this 32-bit
32-bit
address space, so that from a programming point of view, the Blackfin
Blackfin
has a Von Neumann architecture. The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses, designed for higher sustained data rates between the core and L1 memory. Portions of instruction and data L1 SRAM can be optionally configured as cache independently. Certain Blackfin
Blackfin
processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2. Blackfin
Blackfin
processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR flash, NAND flash and SRAM. Some Blackfin processors also include mass-storage interfaces such as ATAPI and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space. Coupled with the core and memory system is a DMA engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel
DMA channel
for each peripheral, which is designed for higher throughput for applications that can utilise it, such as real-time standard-definition (D1) video encoding and decoding. Microcontroller
Microcontroller
features[edit] The architecture of Blackfin
Blackfin
contains the usual CPU, memory, and I/O that is found on microprocessors or microcontrollers. These features enable operating systems. All Blackfin
Blackfin
processors contain a Memory Protection Unit (MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin
Blackfin
to support operating systems, RTOSs and kernels like ThreadX, µC/OS-II, or NOMMU Linux. Although the MPU is referred to as a Memory Management Unit (MMU) in the Blackfin
Blackfin
documentation, the Blackfin
Blackfin
MPU does not provide address translation like a traditional MMU, so it does not support virtual memory or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or QNX. Blackfin
Blackfin
supports three run-time modes: supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc.) an exception will be thrown and the kernel will then be able to shut down the offending thread/process. The official guidance from ADI on how to use the Blackfin
Blackfin
in non-OS environments is to reserve the lowest-priority interrupt for general-purpose code so that all software is run in supervisor space. Blackfin
Blackfin
uses a variable-length RISC-like instruction set consisting of 16-, 32- and 64-bit instructions. Commonly used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32- and 64-bit opcodes. This variable length opcode encoding is designed for code density equivalence to modern microprocessor architectures. Media-processing features[edit] The Blackfin
Blackfin
instruction set contains media-processing extensions to help accelerate pixel-processing operations commonly used in video compression and image compression and decompression algorithms. Peripherals[edit]

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Blackfin
Blackfin
processors contain an array of connectivity peripherals, depending on the specific processor:

ATAPI CAN: A wide-area, low-speed serial bus used in some automotive and industrial electronics DMA with support for memory-to-memory DMA and peripheral DMA EMAC ( Ethernet
Ethernet
Media Access Controller) with MII and RMII GPIO
GPIO
including level-triggered and edge-triggered interrupts I²C, also known as TWI (Two-Wire Interface): a lower speed, shared serial bus MXVR: a MOST Network Interface Controller PPI: A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 75 MHz and can be configured from 8 to 16-bits wide. PWM and timers/counters Real time clock SD/SDIO SPI: a fast serial bus used in some high-speed embedded electronics applications SPORT: A synchronous, high speed serial port that can support TDM, I²S and a number of other configurable framing modes for connection to ADCs, DACs, other processors, FPGAs, etc. UART: allows for bi-directional communication with RS232
RS232
devices (PCs, modems, PC peripherals, etc.), MIDI
MIDI
devices, IRDA devices USB 2.0 OTG (On-The-Go) Watchdog timer

All of the peripheral control registers are memory-mapped in the normal address space. Development tools[edit]

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Blackfin
Blackfin
BF537 EZ-Kit-Lite evaluation platform

ADI provides its own software development toolchains. The original VisualDSP++ IDE is still supported (its last release was 5.1.2 in October 2014; 3 years ago (2014-10)), but is approaching end of life and has not had support added for the new BF6xx and BF7xx processors. The newer toolchain is CrossCore Embedded Studio, which uses upgraded versions of the same compiler and tools internally, but with a UI based on Eclipse CDT. No free version of either tool is available; a single-user license for VisualDSP++ costs $3500 USD, and CrossCore Embedded Studio $995 USD. Other options include Green Hills Software's MULTI IDE, the GNU GCC Toolchain for the Blackfin
Blackfin
processor family, the OpenEmbedded project, National Instruments' LabVIEW
LabVIEW
Embedded Module, or Microsoft Visual Studio through use of AxiomFount's AxiDotNet software. Supported operating systems, RTOSs and kernels[edit]

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Several commercial and open-source operating systems support running on Blackfin.

OS/RTOS/Kernels on Blackfin

Title License Comments

ThreadX[5] Proprietary

Nucleus Proprietary

µC/OS-II[6] Proprietary

INTEGRITY[7] Proprietary

RTEMS GNU General Public License

RTXC Quadros Proprietary

VDK Proprietary ADI's real-time kernel. Ships with VisualDSP++.

.NET Micro Framework Apache License 2.0 Stand-alone version from Microsoft. Integrated version from AxiomFount.

Blackfin
Blackfin
was previously supported by μClinux and later by Linux
Linux
with the NOMMU feature, but as it was not ever widely used and no longer had a maintainer,[8][9] support was removed from Linux
Linux
on the day of the release of version 4.16; 4.17 will be the first release to not include Blackfin
Blackfin
support any longer.[10][11][12] See also[edit]

SHARC TigerSHARC

References[edit]

^ "Archived copy". Archived from the original on April 17, 2011. Retrieved April 9, 2011.  ^ "H.264 BP/MP Encoder". Analog Devices. Retrieved 2014-09-03.  ^ "H.264 BP/MP Decoder Library". Analog Devices. Retrieved 2014-09-03.  ^ " Blackfin
Blackfin
Processors Analog Devices". Analog.com. Retrieved 2016-06-24.  ^ "Real-Time Operating Systems for Embedded Development, Real Time System By Express Logic". Rtos.com. Archived from the original on 2016-05-23. Retrieved 2016-06-24.  ^ "Real-Time Kernels". Micrium.com. Retrieved 2016-06-24.  ^ "INTEGRITY Real-time Operating System". Ghs.com. Retrieved 2016-06-24.  ^ [1] MAINTAINERS: mark arch/blackfin/ and its gubbins as orphaned ^ [2] RE: MAINTAINERS: mark arch/blackfin/ and its gubbins as orphaned ^ [3] arch: remove obsolete architecture ports ^ Simon Sharwood (2018-04-03). " Linux
Linux
4.16 arrives, erases eight CPUs". theregister.co.uk. Retrieved 2018-04-03.  ^ Arnd Bergmann (2018-04-03). "[GIT PULL] arch: remove obsolete architecture ports". LKML. Retrieved 2018-04-04. 

External links[edit]

Blackfin
Blackfin
processor website Blackfin
Blackfin
Processor Programming Reference blackfin.uclinux.org Open source tools and Linux
Linux
kernel for Blackfin T2 SDE A build-system supporting the cross compilation to Blackfin

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