Planar process

The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which silicon integrated circuit chips are built. The process utilizes the surface passivation and thermal oxidation methods.

The planar process was developed at Fairchild Semiconductor in 1959.

Overview

The key concept is to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allows the use of a series of exposures on a substrate (silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization, and the concepts of p–n junction isolation and surface passivation, it is possible to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO₂) oxidation, SiO₂ etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO₂ layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

History

Development

At a 1958 Electrochemical Society meeting, Mohamed Atalla presented a paper about the surface passivation of PN junctions by thermal oxidation, based on his 1957 BTL memos.

Swiss engineer Jean Hoerni attended the same 1958 meeting, and was intrigued by Atalla's presentation. Hoerni came up with the "planar idea" one morning while thinking about Atalla's device. Taking advantage of silicon dioxide's passivating effect on the silicon surface, Hoerni proposed to make transistors that were protected by a layer of silicon dioxide. This led to the first successful product implementation of the Atalla silicon transistor passivation technique by thermal oxide.

The planar process was developed by Jean Hoerni, one of the " traitorous eight", while working at Fairchild Semiconductor, with a first patent issued 1959.

Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

In 1959, Robert Noyce built on Hoerni's work with his conception of an integrated circuit (IC), which added a layer of metal to the top of Hoerni's basic structure to connect different components, such as transistors, capacitors, or resistors, located on the same piece of silicon. The planar process provided a powerful way of implementing an integrated circuit that was superior to earlier conceptions of the integrated circuit. Noyce's invention was the first monolithic IC chip.

Early versions of the planar process used a photolithography process using near-ultraviolet light from a mercury vapor lamp.
As of 2011, small features are typically made with 193 nm "deep" UV lithography.
Shannon Hill
"UV Lithography: Taking Extreme Measures"
National Institute of Standards and Technology (NIST). As of 2022, the ASML NXE platform uses 13.5 nm EUV light, generated by a tin-based plasma source.

See also

*Semiconductor device fabrication

References

External links

* A compendium of articles and other information on the development of integrated circuits, including th
development of oxide masking
th

th

and th



* An overview of the steps in fabrication of an integrated circuit from the Nobel Prize website. This is a section of the wor

{{DEFAULTSORT:Planar Process
Semiconductor device fabrication
Swiss inventions