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Intel Sandy Bridge-based Xeon microprocessors (often referred to as Sandy Bridge-E) are microprocessors based on the
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
's
32 nm The "32 nm" node is the step following the "45 nm" process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technolo ...
Sandy Bridge Sandy Bridge is the List of Intel codenames, codename for Intel's 32 nm process, 32 nm microarchitecture used in the second generation of the Intel Core, Intel Core processors (Intel Core i7, Core i7, Intel Core i5, i5, Intel Core i3, i3). The Sa ...
architecture for servers, workstations, and high-end desktops. It succeeds the six-core
Gulftown Gulftown or Westmere-E is the codename of an up to six-core hyperthreaded Intel processor able to run up to 12 threads in parallel. It is based on Westmere microarchitecture, the 32 nm shrink of Nehalem. Originally rumored to be called the Int ...
/Westmere-EP processor which used the older
LGA 1366 LGA 1366 (land grid array 1366), also known as Socket B, is an Intel CPU socket. This socket supersedes Intel's LGA 775 (Socket T) in the high-end and performance desktop segments. It also replaces the server-oriented LGA 771 (Socket J) in the e ...
package, and uses
LGA 2011 LGA 2011, also called ''Socket R'', is a CPU socket by Intel released on November 14, 2011. It launched along with LGA 1356 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. While LGA 1356 was designed for dual-processor or ...
,
LGA 1356 LGA 1356, also called Socket B2, is an Intel microprocessor socket released in Q1 2012 with 1356 Land Grid Array pins. It launched alongside LGA 2011 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. It's compatible with Intel ...
and
LGA 1155 LGA 1155, also called Socket H2, is a zero insertion force flip-chip land grid array (LGA) CPU socket designed by Intel for their CPUs based on the Sandy Bridge (second generation core) and Ivy Bridge (microarchitecture), Ivy Bridge (third gen ...
socket depending on the package.


Overview

There are five different families of Xeon processors that were based on Sandy Bridge architecture: * Sandy Bridge-E (
LGA 2011 LGA 2011, also called ''Socket R'', is a CPU socket by Intel released on November 14, 2011. It launched along with LGA 1356 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. While LGA 1356 was designed for dual-processor or ...
) targeted high-end desktop (HEDT) enthusiast segment. It was branded as Core i7 Extreme Edition and Core i7 processors, despite sharing many similarities with Xeon models. * Sandy Bridge-EP (
LGA 2011 LGA 2011, also called ''Socket R'', is a CPU socket by Intel released on November 14, 2011. It launched along with LGA 1356 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. While LGA 1356 was designed for dual-processor or ...
) branded as Xeon E5 models aimed at high-end servers and workstations. It supported motherboards equipped with up to 4 sockets. * Sandy Bridge-EN (
LGA 1356 LGA 1356, also called Socket B2, is an Intel microprocessor socket released in Q1 2012 with 1356 Land Grid Array pins. It launched alongside LGA 2011 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. It's compatible with Intel ...
) uses a smaller socket for low-end and dual-processor servers on certain Xeon E5 and Pentium branded models. * Sandy Bridge Xeon (
LGA 1155 LGA 1155, also called Socket H2, is a zero insertion force flip-chip land grid array (LGA) CPU socket designed by Intel for their CPUs based on the Sandy Bridge (second generation core) and Ivy Bridge (microarchitecture), Ivy Bridge (third gen ...
) were mostly identical to its desktop counterparts apart from the missing
IGPU A graphics card (also called a video card, display card, graphics accelerator, graphics adapter, VGA card/VGA, video adapter, display adapter, or colloquially GPU) is a computer expansion card that generates a feed of graphics output to a displa ...
despite branded as Xeon E3 processors. * Gladden (BGA 1284) Xeon E3 models were for embedded applications.
IGPU A graphics card (also called a video card, display card, graphics accelerator, graphics adapter, VGA card/VGA, video adapter, display adapter, or colloquially GPU) is a computer expansion card that generates a feed of graphics output to a displa ...
is absent on most of these processors unless noted otherwise.


Sandy Bridge-E and Sandy Bridge-EP

All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with va ...
, SSE4.2, AVX, Enhanced Intel
SpeedStep Enhanced SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel's microprocessors that allow the clock speed of the processor to be ...
Technology (EIST),
Intel 64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new operating modes: 64-bit mode an ...
, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), TXT,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
, Intel EPT,
Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
Intel VT-c x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware- ...
, Intel x8 SDDC, Hyper-threading (except E5-1603, E5-1607, E5-2603, E5-2609 and E5-4617),
Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units' (CPUs') dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher result ...
(except E5-1603, E5-1607, E5-2603, E5-2609, E5-4603 and E5-4607),
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, Smart Cache.''


Sandy Bridge-EN

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with va ...
, SSE4.2, AVX, Enhanced Intel
SpeedStep Enhanced SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel's microprocessors that allow the clock speed of the processor to be ...
Technology (EIST),
Intel 64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new operating modes: 64-bit mode an ...
, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), TXT,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
, Intel EPT,
Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
,
Intel VT-c x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware- ...
, Intel x8 SDDC, Hyper-threading (except E5-2403 and E5-2407),
Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units' (CPUs') dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher result ...
(except E5-1428L, E5-2403 and E5-2407),
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, Smart Cache.''


Sandy Bridge Xeon

*All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with va ...
, SSE4.2, AVX, Enhanced Intel
SpeedStep Enhanced SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel's microprocessors that allow the clock speed of the processor to be ...
Technology (EIST),
Intel 64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new operating modes: 64-bit mode an ...
, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), TXT,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
, Intel EPT,
Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
, Hyper-threading (except E3-1220 and E3-1225),
Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units' (CPUs') dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher result ...
,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, Smart Cache.'' * All models support uni-processor configurations only. * Intel HD Graphics P3000 uses drivers that are optimized and certified for professional applications, similar to
Nvidia Quadro Quadro was Nvidia's brand for graphics cards intended for use in workstations running professional computer-aided design (CAD), computer-generated imagery (CGI), digital content creation (DCC) applications, scientific calculations and machine l ...
and
AMD FirePro AMD FirePro was AMD's brand of graphics cards designed for use in workstations and servers running professional Computer-aided design (CAD), Computer-generated imagery (CGI), Digital content creation (DCC), and High-performance computing/GPGP ...
products. * Die size: D2: 216 mm², Q0: 131 mm² * Steppings: D2, Q0


Gladden

*BGA 1284 package *All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with va ...
, SSE4.2, AVX, Enhanced Intel
SpeedStep Enhanced SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel's microprocessors that allow the clock speed of the processor to be ...
Technology (EIST),
Intel 64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new operating modes: 64-bit mode an ...
, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), TXT,
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
, Intel EPT,
Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...
, Hyper-threading,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
.'' * All models support uni-processor configurations only. * Die size:216 mm² * Steppings: D2


See also

*
List of Intel chipsets This article provides a list of motherboard chipsets made by Intel, divided into three main categories: those that use the PCI bus for interconnection (the 4xx series), those that connect using specialized "hub links" (the 8xx series), and thos ...
*
List of Intel CPU microarchitectures The following is a ''partial'' list of Intel CPU microarchitectures. The list is ''incomplete'', additional details can be found in Intel's tick–tock model, process–architecture–optimization model and Template:Intel processor roadmap. x86 ...


References


Further reading

* {{Intel processors, bridge Intel microprocessors