SYCL is a higher-level programming model to improve programming productivity on various

hardware accelerators Hardware acceleration is the use of computer hardware designed to perform specific functions more efficiently when compared to software running on a general-purpose central processing unit (CPU). Any transformation of data that can be calcul ...

. It is a single-source embedded domain-specific language (

eDSL A domain-specific language (DSL) is a computer language specialized to a particular application domain. This is in contrast to a general-purpose language (GPL), which is broadly applicable across domains. There are a wide variety of DSLs, ranging ...

) based on pure

C++17 C++17 is a version of the ISO/ IEC 14882 standard for the C++ programming language. C++17 replaced the prior version of the C++ standard, called C++14, and was later replaced by C++20. History Before the C++ Standards Committee fixed a 3-yea ...

. It is a standard developed by

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, announced in March 2014.

Origin of the name

SYCL (pronounced ‘sickle’) is a name and not an

acronym An acronym is a word or name formed from the initial components of a longer name or phrase. Acronyms are usually formed from the initial letters of words, as in '' NATO'' (''North Atlantic Treaty Organization''), but sometimes use syllables, a ...

. In particular, SYCL developers made clear that the name contains no reference to

OpenCL OpenCL (Open Computing Language) is a framework for writing programs that execute across heterogeneous platforms consisting of central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field-prog ...

Purpose

SYCL is a royalty-free, cross-platform abstraction layer that builds on the underlying concepts, portability and efficiency inspired by

that enables code for heterogeneous processors to be written in a “single-source” style using completely standard C++. SYCL enables single-source development where C++ template functions can contain both host and device code to construct complex algorithms that use

, and then re-use them throughout their source code on different types of data. While the SYCL standard started as the higher-level programming model sub-group of the

working group and was originally developed for use with

and SPIR, SYCL is a

workgroup independent from the

working group since September 20, 2019 and starting with SYCL 2020, SYCL has been generalized as a more general heterogeneous framework able to target other systems. This is now possible with the concept of a generic backend to target any acceleration API while enabling full interoperability with the target API, like using existing native libraries to reach the maximum performance along with simplifying the programming effort. For example, the hipSYCL implementation targets ROCm and

CUDA CUDA (or Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for general purpose processing, an approach ...

via AMD's cross-vendor HIP.

Versions

SYCL was introduced at GDC in March 2014 with provisional version 1.2, then the SYCL 1.2 final version was introduced at IWOCL 2015 in May 2015. The latest version for the previous SYCL 1.2.1 series is SYCL 1.2.1 revision 7 which was published on April 27, 2020 (the first version was published on December 6, 2017). SYCL 2.2 provisional was introduced at IWOCL 2016 in May 2016 targeting C++14 and

2.2. But the SYCL committee preferred not to finalize this version and to move towards a more flexible SYCL specification to address the increasing diversity of current

, including

artificial intelligence Artificial intelligence (AI) is intelligence—perceiving, synthesizing, and inferring information—demonstrated by machine A machine is a physical system using Power (physics), power to apply Force, forces and control Motion, moveme ...

engines, which led to SYCL 2020. The latest version is SYCL 2020 revision 6 which was published on November 13, 2022, an evolution from first release of revision 2 which was published on February 9, 2021, taking into account the feedback from users and implementors on the SYCL 2020 Provisional Specification revision 1 published on June 30, 2020. C++17 and OpenCL 3.0 support are main targets of this release. Unified shared memory (USM) is one main feature for GPUs with OpenCL and CUDA support. At IWOCL 2021 a roadmap was presented. DPC++, ComputeCpp, hipSYCL, triSYCL and neoSYCL are the main implementations of SYCL. Next Target in development is support of C++20 in future SYCL 202x.

Implementations

* DPC++: (data parallel C++) is an open source project of Intel to introduce SYCL for LLVM and oneAPI. C++17 and parts of C++20 with SYCL 2020 are base of this Compiler framework. * ComputeCpp: SYCL 1.2.1 conformant framework of firm Codeplay with community version * hipSYCL: incomplete 1.2.1 support without OpenCL coupling and images, partly SYCL 2020, supports ROCm (AMD), CUDA (Nvidia), OpenMP (CPUs) and Level Zero (Intel). Actual Version is 0.9.1 in March 2021. * triSYCL: based on C++20, OpenMP and OpenCL, slow development, incomplete, with a version based on top of DPC++ * neoSYCL: SYCL 1.2.1 nearly complete, for hpc SX-Aurora Tsubasa, no OpenCL specific features like image support * SYCL-gtx: C++11 support, for OpenCL 1.2+, far from complete, no actual development * Sylkan is an implementation of SYCL to Vulkan devices in an experimental state. * Polygeist has a fork compiling SYCL through MLIR which is backed by the Inteon company.

Software

* Gromacs: SYCL 2020 is Part of Gromacs Version 2021. * use in automotive Industrie for autonomous driving with support of ISO 26262.

Tutorials

There are a few tutorials in the ComputeCpp SYCL guides.

License

The source files for building the specification, such as Makefiles and some scripts, the SYCL headers and the SYCL code samples are under the Apache 2.0 license. Details of the license are at: https://www.apache.org/licenses/LICENSE-2.0.html

Comparison with other APIs

The open standards SYCL and

are similar to the programming models of the proprietary stack

from

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, and HIP from the open-source stack ROCm, supported by AMD. In the

realm,

and Vulkan are the low-level ''non-single source'' API and SYCL is the high-level ''single-source'' C++

embedded domain-specific language A domain-specific language (DSL) is a computer language specialized to a particular application domain. This is in contrast to a general-purpose language (GPL), which is broadly applicable across domains. There are a wide variety of DSLs, ranging ...

(eDSL).

CUDA

By comparison, the ''single-source'' C++

version of CUDA, which is actually named "CUDA ''Runtime'' API", is somewhat similar to SYCL. But there is actually a less known ''non single-source'' version of CUDA which is called "CUDA ''Driver'' API", similar to

, and used for example by the CUDA ''Runtime'' API implementation itself. SYCL extends the C++ AMP features relieving the programmer from explicitly transferring the data between the host and devices by using ''buffers'' and ''accessors'', by opposition to CUDA (before the introduction of ''Unified Memory'' in CUDA 6). But starting with SYCL 2020, it is also possible to use USM instead of ''buffers'' and ''accessors'' to use a lower-level programming model similar to ''Unified Memory'' in CUDA. SYCL is higher-level than C++ AMP and CUDA since you do not need to build an explicit dependency graph between all the kernels, and provides you automatic asynchronous scheduling of the kernels with communication and computation overlap. This is all done by using the concept of accessors, without requiring any compiler support. Unlike C++ AMP and CUDA, SYCL is a pure C++ eDSL without any C++ extension, allowing a basic CPU implementation relying on pure runtime without any specific compiler. This is very useful for debugging an application or for prototyping for a new architecture without having the architecture and compiler available yet. There are at least 3 known SYCL implementations targeting the CUDA backend.

ROCm HIP

ROCm HIP can be seen as a clone of CUDA targeting Nvidia GPU, AMD GPU and x86 CPU. Thus ROCm HIP is a lower-level API compared to SYCL and most of the comments mentioned in the comparison with CUDA do apply. ROCm HIP has some similarities to SYCL in the sense that it can target various vendors (AMD and Nvidia) and accelerator types (GPU and CPU). But SYCL can target according to the implementation any type of accelerators and any vendors, potentially at the same time, in a single application with the concept of backend. SYCL is also pure C++ while HIP uses some extensions inherited from CUDA, which prevents using a normal C++ compiler to target any CPU. There are at least 2 known implementations of SYCL targeting the HIP backend, oneAPI DPC++ and hipSYCL. Th
hipSYCL
implementation, over HIP, adds SYCL programming to CUDA and HIP.

Other programming models

SYCL has many similarities to the Kokkos programming model, including the use of opaque multi-dimensional array objects (SYCL buffers and Kokkos arrays), multi-dimensional ranges for parallel execution, and reductions (added in SYCL 2020). Numerous features in SYCL 2020 were added in response to feedback from the Kokkos community.

References

External links

Khronos SYCL webpage

The SYCL specifications in Khronos registry

C++17 ParallelSTL in SYCL

SYCL tech resources

Codeplay ComputeCpp SYCL implementation

Implementation of SYCL started by Intel with the goal of Clang/LLVM up-streaming

hipSYCL: implementation of SYCL 1.2.1 over AMD HIP/NVIDIA CUDA

triSYCL open-source SYCL implementation

SYCL Conference @ IWOCL

"SYCL 2020 Launches with New Name, New Features, and High Ambition", HPCWire article (2021 Feb. 9th)

James Reinders, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, Xinmin Tian: "Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL", Apress (2021), OpenAccess.
{{Parallel computing Application programming interfaces C++ Cross-platform software Domain-specific programming languages GPGPU

Heterogeneous computing Parallel computing