List Of AMD Opteron Microprocessors
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Opteron is a
central processing unit A central processing unit (CPU), also called a central processor, main processor, or just processor, is the primary Processor (computing), processor in a given computer. Its electronic circuitry executes Instruction (computing), instructions ...
(CPU) family within the AMD64 line. Designed by Advanced Micro Devices (AMD) for the server market, Opteron competed with Intel's Xeon. The Opteron family is succeeded by the Zen-based Epyc, and Ryzen Threadripper and Threadripper Pro series. For Socket 940 and Socket 939 Opterons, each chip has a three-digit model number, in the form ''Opteron XYY''. For Socket F and Socket AM2 Opterons, each chip has a four-digit model number, in the form ''Opteron XZYY''. For all Opterons, the first digit (the X) specifies the number of CPUs on the target machine: * 1 – has 1 processor (uniprocessor) * 2 – has 2 processors (dual processor) * 8 – has 4 or 8 processors For Socket F and Socket AM2 Opterons, the second digit (the Z) represents the processor generation. Presently, only 2 (dual-core), DDR2, 3 (quad-core) and 4 (six-core) are used. For all Opterons, the last two digits in the model number (the YY) indicate the clock rate (frequency) of a CPU, a higher number indicating a higher clock rate. This speed indication is comparable to processors of the same generation if they have the same amount of cores. Single-cores and dual-cores have different indications, despite sometimes having the same clock rate. Model number methodology for the AMD Opteron 4000 and 6000 Series processors.
AMD Opteron processors are identified by a four digit model number, ''ZYXX'', where:
Z – denotes product series * 4000 Series = Low cost and power optimized 1- and 2-way servers * 6000 Series = High performance 2- and 4-way servers Y – denotes series generation * 41xx = 1st generation of 4000 series * 61xx = 1st generation of 6000 series XX – communicates a change in product specifications within the series, and is not a relative measure of performance. The suffix HE or EE denotes a high-efficiency or energy-efficiency model with a lower thermal design power (TDP) than a standard Opteron. The suffix SE denotes a top-of-the-line model with a higher TDP than a standard Opteron.


Feature overview


CPUs


APUs

APU features table


K8 Opterons (Family 0Fh)


First Gen. Opterons (130 nm)


100 series "SledgeHammer"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models with OPN ending in AG support up to Registered PC2700 DDR SDRAM * All other models support up to Registered PC3200 DDR SDRAM * All models only support single-processor configurations


200 series "SledgeHammer"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models with OPN ending in AH support up to Registered PC2700 DDR SDRAM * All other models support up to Registered PC3200 DDR SDRAM * All models support up to two-processor configurations


800 series "SledgeHammer"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models with OPN ending in AI support up to Registered PC2700 DDR SDRAM * All other models support up to Registered PC3200 DDR SDRAM * All models support up to eight-processor configurations


First Gen. Opterons (90 nm)


100 series "Venus" (s939)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models support up to Unbuffered PC3200 DDR SDRAM * All models only support single-processor configurations


100 series "Venus"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models support up to Registered PC3200 DDR SDRAM * All models only support single-processor configurations


200 series "Troy"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models support up to Registered PC3200 DDR SDRAM * All models support up to two-processor configurations


800 series "Athens"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models support up to Registered PC3200 DDR SDRAM * All models support up to eight-processor configurations


Dual-core Opteron (90 nm)


100 series "Denmark" (s939)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models support up to Unbuffered PC3200 DDR SDRAM * All models only support single-processor configurations


200 series "Italy"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models support up to Registered PC3200 DDR SDRAM * All models support up to two-processor configurations


800 series "Egypt"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64'' * All models support up to Registered PC3200 DDR SDRAM * All models support up to eight-processor configurations


Second Gen. Opterons (90nm)


1200 series "Santa Ana"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64, AMD-V'' * All models support up to Unbuffered PC2-6400 DDR2 SDRAM, the socket F 1210 EE model supports Registered DDR2 memory * All models only support single-processor configurations


2200 series "Santa Rosa"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64, AMD-V'' * All models support up to Registered PC2-5300 DDR2 SDRAM * All models support up to two-processor configurations


8200 series "Santa Rosa"

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced 3DNow!, NX bit, AMD64, AMD-V'' * All models support up to Registered PC2-5300 DDR2 SDRAM * All models support up to eight-processor configurations


K10 Opterons (Family 10h)


Quad-core Opteron (65nm)

* All models support the x86-64 "baseline" profile * All models support additionally: ''Enhanced 3DNow!'', ''
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
'', '' SSE4a'', '' ABM'', '' NX bit'', '' AMD-V'' with nested paging


1300 series "Budapest"

* Socket AM2+ platform, single-processor only * All models support up to dual-channel Unbuffered PC2-6400 DDR2 SDRAM * B1 and B2 steppings have a hardware TLB bug, affecting performance under certain conditions, see AMD errata #298


2300 series "Barcelona"

* Socket F platform * All models support up to two-processor configurations * All models support up to dual-channel Registered PC2-5300 DDR2 SDRAM * B1 and B2 steppings have a hardware TLB bug, affecting performance under certain conditions, see AMD errata #298


8300 series "Barcelona"

* Socket F platform * All models support up to eight-processor configurations * All models support up to dual-channel Registered PC2-5300 DDR2 SDRAM * B1 and B2 steppings have a hardware TLB bug, affecting performance under certain conditions, see AMD errata #298


Quad-core Opteron (45nm)

* All models support the x86-64 "baseline" profile * All models support additionally: ''Enhanced 3DNow!'', ''
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
'', '' SSE4a'', '' ABM'', '' NX bit'', '' AMD-V'' with nested paging


1300-series "Suzuka"

* Socket AM3 platform, Socket F for select models, single-processor only * Socket AM3 models support up to dual-channel Unbuffered PC3-10600 DDR3 SDRAM * Socket F models support up to dual-channel Registered PC2-6400 DDR2 SDRAM


2300 series "Shanghai"

* Socket F platform * All models support up to two-processor configurations * All models support up to dual-channel Registered PC2-6400 DDR2 SDRAM


8300 series "Shanghai"

* Socket F platform * All models support up to eight-processor configurations * All models support up to dual-channel Registered PC2-6400 DDR2 SDRAM


Six-core Opteron (45 nm)

* All models support the x86-64 "baseline" profile * All models support additionally: ''Enhanced 3DNow!'', ''
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
'', '' SSE4a'', '' ABM'', '' NX bit'', '' AMD-V'' with nested paging * All models support ''HT Assist'' which reduces cache coherence snoops traffic. When enabled, 1 MiB of L3 cache on each chip is used as a cache coherence directory.


2400 series "Istanbul"

* Socket F platform * All models support up to two-processor configurations * All models support up to dual-channel Registered PC2-6400 DDR2 SDRAM


8400 series "Istanbul"

* Socket F platform * All models support up to eight-processor configurations * All models support up to dual-channel Registered PC2-6400 DDR2 SDRAM


C32 & G34 (45 nm)

* All models support the x86-64 "baseline" profile * All models support additionally: ''Enhanced 3DNow!'', ''
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
'', '' SSE4a'', '' ABM'', '' NX bit'', '' AMD-V'' with nested paging * All models support ''HT Assist'' to reduce cache coherence snooping traffic. When enabled, 1 MiB of L3 cache on each chip is used as a cache coherence directory.


4100 series "Lisbon"

* Socket C32 platform * All models support up to two-processor configurations * All models support up to dual-channel Registered PC3-10600 DDR3 SDRAM


6100 series "Magny-Cours"

* Socket G34 platform * All models use a Multi-Chip module (MCM) design with two dies in each package * All models support up to four-processor configurations * All models support up to four-channel Registered PC3-10600 DDR3 SDRAM


Bulldozer based Opterons


3200-, 4200- & 6200-series Opterons


Opteron 3200-series "Zurich" (32 nm)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, SSE4a, IOMMU, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, CVT16– F16C, XOP, FMA4.'' * All models support single socket configurations * Memory support: Up to 4 DIMMs per socket * Memory controller: Two channels of UDDR3, RDDR3 up to PC3-15000 * Die size: 315 mm2


Opteron 4200-series "Valencia" (32 nm)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA4.'' * All models support up to two socket configurations * Memory support: Up to 4 DIMMs per socket * Memory controller: Two channels of UDDR3, RDDR3 up to PC3-12800


Opteron 6200-series "Interlagos" (32 nm)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA4.'' * All models support two or four socket configurations * Memory support: Up to 12 DIMMs per socket * Memory controller: Four channels of UDDR3, RDDR3 up to PC3-12800 * Interlagos models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.


Piledriver based Opterons


3300-, 4300- & 6300-series Opterons


Opteron 3300-series "Delhi" (32 nm)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, CVT16– F16C, AMD Turbo Core3.0., ECC'' * All models support single socket configurations * Memory support: Up to 4 DIMMs per socket * Memory controller: Two channels of UDDR3, RDDR3 up to PC3-15000 * Die size: 315 mm2


Opteron 4300-series "Seoul" (32 nm)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, CVT16– F16C, AMD Turbo Core, ECC'' * All models support up to two socket configurations * Memory support: Up to 4 DIMMs per socket * Memory controller: Two channels of UDDR3, RDDR3 up to PC3-15000


Opteron 6300-series "Abu Dhabi" (32 nm)

* All models support: '' MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, IOMMU, AES, CLMUL, AVX, AVX 1.1, BMI1 (Bit Manipulation Instructions 1), ABM (Advanced Bit Manipulation), TBM (Trailing Bit Manipulation instructions), XOP, FMA3, FMA4, CVT16– F16C, Turbo Core 2.0, EVP (Enhanced Virus Protection), ECC'' * All models support two or four socket configurations * Memory support: Up to 12 DIMMs per socket * Memory controller: Four channels of UDDR3, RDDR3 up to PC3-15000 * Abu Dhabi models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache. * Two new 6300 models code-named "Warsaw" were added in 2014 (6338P and 6370P) that operate at lower clock frequencies using less power.


Excavator based Opterons


X3000-series Opterons


Opteron X3000-series "Toronto" (28 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1,
AVX2 Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then Sandy Bridge New Instructions) are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They w ...
, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND * Two or Four CPU cores based on the
Excavator Excavators are heavy equipment (construction), heavy construction equipment primarily consisting of a backhoe, boom, dipper (or stick), Bucket (machine part), bucket, and cab on a rotating platform known as the "house". The modern excavator's ...
microarchitecture * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * Memory controller: Two channels of DDR4 SDRAM up to PC4-19200 * GPU based on Graphics Core Next (GCN) 3rd Generation architecture


Jaguar-based Opterons


X1100 and X2100 series Opterons


Opteron X1100-series "Kyoto" (28nm)

* Socket FT3 (BGA) * 4 CPU cores ( Jaguar (microarchitecture)) * SSE4.1, SSE4.2, AVX, AES, F16C, BMI1, AMD-V, AMD-P (power management) support * Turbo Dock Technology, C6 and CC6 low power states * 128-bit FPU


Opteron X2100-series "Kyoto" (28nm)

* Socket FT3 (BGA) * 4 CPU cores ( Jaguar (microarchitecture)) * SSE4.1, SSE4.2, AVX, AES, F16C, BMI1 support * Turbo Dock Technology, C6 and CC6 low power states * GPU based on Graphics Core Next (GCN) architecture


ARM Cortex A57 based Opterons


Opteron A1100-series "Seattle" (28nm)

The AMD Opteron A1100 is an enterprise-class ARM Cortex-A57-based SOC. * Up to 64 GB DDR3L-1600 and up to 128GB DDR4-1866 with ECC * SoC peripherals include 6 × SATA 3, 2 × Integrated 10 GbE LAN and 8 PCI Express lanes in ×8, ×4 and ×2 configurations.


See also

* List of AMD chipsets * List of AMD processors with 3D graphics * List of AMD Epyc microprocessors * List of AMD FX microprocessors * Table of AMD processors


References


External links

*
AMD Technical Docs
{{AMD CPU sockets *Opteron AMD Opteron