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Intel Atom Intel Atom is a line of IA-32 and x86-64 instruction set ultra-low-voltage processors by Intel Corporation designed to reduce electric consumption and power dissipation in comparison with ordinary processors of the Intel Core series. Atom is m ...
is
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
's line of low-power, low-cost and low-performance
x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel, based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. Th ...
and
x86-64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set architecture, instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new ope ...
microprocessor A microprocessor is a computer processor (computing), processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, a ...
s. Atom, with codenames of '' Silverthorne'' and '' Diamondville'', was first announced on March 2, 2008. For nettop and netbook Atom microprocessors after ''Diamondville'', the memory and graphics controller are moved from the northbridge to the CPU. This explains the drastically increased transistor count for post-''Diamondville'' Atom microprocessors.


Nettop A mini PC (or miniature PC, nettop, or Smart Micro PC) is a small-sized, inexpensive, low-power, Legacy free PC, legacy-free desktop computer, desktop computer designed for basic tasks such as Web navigation, web browsing, accessing web appl ...
processors (small desktop)


Bonnell microarchitecture


" Diamondville" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading * Transistors: 47 million * Die size: 25.96 mm2 (3.27 × 7.94) * Package size: 22 mm × 22 mm


" Pineview" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading * Integrated GMA 3150 GPU and DDR3/DDR2 single-channel memory controller * Transistors: 123 million (single-core), 176 million (dual-core) * Die size: 66 mm2 (9.56 × 6.89) (single-core), 87 mm2 (9.56 × 9.06) (dual core) * Package size: 22 mm × 22 mm


Saltwell microarchitecture


" Cedarview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading (except D2500) * Integrated PowerVR SGX545-based Intel GMA 3600/ GMA 3650 GPU and DDR3 single-channel memory controller * Package size: 22 mm × 22 mm


Netbook A netbook is a small-sized laptop computer; they were primarily sold from 2007 until around 2013, designed mostly as a means of accessing the Internet and being significantly less expensive than regular-sized laptops. At their inception in l ...
processors (sub-notebook)


Bonnell microarchitecture


" Diamondville" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading * Transistors: 47 million * Die size: 26 mm2 * Package size: 22 mm × 22 mm


" Pineview" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Intel 64, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading * Integrated GMA 3150 GPU and DDR3/DDR2 single-channel memory controller supporting up to 2 GB * Transistors: 123 million (single-core), 176 million (dual-core) * Die size: 66 mm2 (9.56 × 6.89) (single-core), 87 mm2 (9.56 × 9.06) (dual core) * Package size: 22 mm × 22 mm


Saltwell microarchitecture


" Cedarview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Intel 64, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading * Integrated PowerVR SGX545-based Intel GMA 3600/ GMA 3650 GPU and DDR3 single-channel memory controller * Package size: 22 × 22 mm


MID processors/SoCs (

UMPC An ultra-mobile PC, or ultra-mobile personal computer (UMPC), is a miniature version of a Pen computing, pen computer, a class of laptop whose specifications were launched by Microsoft and Intel in Spring 2006. Sony had already made a first at ...
/
Smartphone A smartphone is a mobile phone with advanced computing capabilities. It typically has a touchscreen interface, allowing users to access a wide range of applications and services, such as web browsing, email, and social media, as well as multi ...
/ IoT)


Bonnell microarchitecture


" Silverthorne" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading * Models Z520, Z520PT, Z530, Z530P, Z540, Z550 and Z560 support Intel VT-x * Model Z515 supports ''Intel Burst Performance Technology'' * Uses the Poulsbo chipset. * Transistors: 47 million * Die size: 26 mm2 * Package size: 13 mm × 14 mm / 22 mm × 22 mm (processors ending with the ''P'' or ''PT'' sSpec number)


" Lincroft" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading. All except Z605 support Intel Burst Performance Technology (BPT). * GMA 600 GPU and DDR2 single-channel memory controller are integrated into the processor. * Transistors: 140 million * Die size: 7.34 mm × 8.89 mm = 65.2526 mm2 * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings: C0


Saltwell microarchitecture


" Penwell" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel Burst Performance Technology (BPT), Hyper-Threading. * Integrated PowerVR SGX540 GPU and DDR3 single-channel memory controller * Package size: 12 mm × 12 × 1.0 mm * Transistors: 140 million * Die size: 65.2526 mm2 (7.34 mm x 8.89 mm)


Silvermont microarchitecture


" Merrifield" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, Intel Burst Performance Technology (BPT). * Z3480 also supports Intel Wireless Display. * Integrated PowerVR G6400 GPU, memory controller supporting two 32-bit LPDDR3 channels up to 4 GB, USB 3.0 controller, eMMC 4.5 * Paired with Intel XMM 7160 LTE modem supporting 4G/3G/2G * Package size: 12 mm × 12 × 1.0 mm


" Moorefield" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, Intel Burst Performance Technology (BPT), Intel Wireless Display. * GPU ( PowerVR G6430) and memory controller are integrated onto the processor die * Package size: 14 mm × 14 × 1.0 mm


"

SoFIA Sofia is the Capital city, capital and List of cities and towns in Bulgaria, largest city of Bulgaria. It is situated in the Sofia Valley at the foot of the Vitosha mountain, in the western part of the country. The city is built west of the Is ...
" (28 nm)

* SoFIA (''smart or feature phone with Intel architecture'') * All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;< ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel Burst Performance Technology (BPT), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
(based on Silvermont's specs) * GPU ( ARM Mali) and memory controller are integrated onto the processor die * Package size: 34 × 40 mm * SoFIA 3G SoC with Silvermont CPU **Integrated HSPA+ A-GOLD 620: 2G/3G RF, CNV, PMU, Audio (Atom x3-C3130) Rockchip#Tablet processors with integrated modem * SoFIA 3G–R SoC with Silvermont CPU **Integrated HSPA+ A-GOLD 620: 2G/3G RF, CNV, PMU, Audio (Atom x3-C3230RK) * SoFIA LTE (W) with Airmont CPU (Announced, but never launched) **Integrated LTE Cat. 4 (XG726-based), SMARTi 4.5, LnP/ CG2000, PMIC (Atom x3-C3440 & C3445)


Tablet processors/SoCs


Bonnell microarchitecture


" Lincroft" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading. All except Z605 support Intel Burst Performance Technology (BPT). * GMA 600 GPU and DDR2 single-channel memory controller are integrated onto the processor die * Transistors: 140 million * Die size: 7.34 mm × 8.89 mm = 65.2526 mm2 * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings: C0


Saltwell microarchitecture


" Cloverview" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Hyper-Threading, Intel Burst Performance Technology (BPT). * GPU and memory controller are integrated onto the processor die * Package size: 13.8 mm × 13.8 × 1.0 mm * Steppings:B1, C0 No official TDP available. For power data see page 129–130.


Silvermont microarchitecture


" Bay Trail-T" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;< ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel Burst Performance Technology (BPT), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, TXT/TXE * Package size: 17 mm × 17 × 1.0 mm Type 4 SoC:Data sheet
Intel * DDR3L single-channel or LPDDR3 dual-channel memory controller supporting up to 4 GB; ECC supported in single-channel mode * Display controller with 2 MIPI DSI ports and 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a) * Integrated Intel HD Graphics (Gen7) GPU * One USB 3.0 controller supporting one USB 3.0 port (can be multiplexed to support four USB 2.0 ports) * One USB 2.0 controller supporting four ports * Integrated LPE audio controller * Integrated image signal processor supporting two MIPI CSI ports, 24 MP sensors, and stereoscopic video * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM Type 3 SoC: * DDR3L/L-RS single-channel memory controller supporting up to 2 GB * Display controller with 1 MIPI DSI port and 2 DDI ports (HDMI 1.4) * Integrated Intel HD Graphics (Gen7) GPU * One USB controller supporting two USB 2.0 ports * Integrated LPE audio controller * Integrated image signal processor supporting two MIPI CSI ports and 8 MP sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Airmont microarchitecture


" Cherry Trail-T" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;< ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x2 (VT-x with EPT, FlexMigration, FlexPriority and VPID
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
., TXT/TXE * Package size: 17 mm × 17 × 1.0 mm Type 4 SoC: * LPDDR3 dual-channel memory controller supporting up to 8 GB * PCI Express 2.0 controller with 2 lanes * Display controller with 2 MIPI DSI ports and 3 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen8) GPU * One USB xHCI controller supporting three USB 3.0 ports, two SSCI ports, and two HSIC ports * One USB xDCI controller supporting one USB 3.0 port * Integrated LPE audio controller * Integrated image signal processor supporting three MIPI CSI ports and 13 MP ZLS sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM Type 3 SoC: * DDR3L/L-RS single-channel memory controller supporting up to 2 GB * PCI Express 2.0 controller with 1 lane * Display controller with 2 MIPI DSI ports and 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen8) GPU * One USB controller supporting three USB 2.0 ports and two HSIC ports * Integrated LPE audio controller * Integrated image signal processor supporting three MIPI CSI ports and 8 MP sensors * Integrated memory card reader supporting SDIO 3.0, eMMC 4.51, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Embedded processors/ SoCs


Bonnell microarchitecture


" Tunnel Creek" (45 nm)

* CPU core supports
IA-32 IA-32 (short for "Intel Architecture, 32-bit", commonly called ''i386'') is the 32-bit version of the x86 instruction set architecture, designed by Intel and first implemented in the i386, 80386 microprocessor in 1985. IA-32 is the first incarn ...
architecture, MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), hyper-threading, Intel VT-x. * Package size: 22 mm × 22 mm * Steppings: B0 * Temperature range: for (E620, E640, E660, E680): 0 °C to +70 °C, for (E620T, E640T, E660T, E680T): -40 °C to +85 °C. * DDR2 single-channel memory controller supporting up to 2 GB * PCI Express 1.0a controller with 4 lanes * Display controller with LVDS and serial DVO ports * Integrated GMA600 (PowerVR) GPU * Integrated HD audio controller * Serial I/O supporting SPI


" Stellarton" (45 nm)

* " Tunnel Creek" CPU with an Altera Field Programmable Gate Array (FPGA) * CPU core supports
IA-32 IA-32 (short for "Intel Architecture, 32-bit", commonly called ''i386'') is the 32-bit version of the x86 instruction set architecture, designed by Intel and first implemented in the i386, 80386 microprocessor in 1985. IA-32 is the first incarn ...
architecture, MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), Hyper-Threading, Intel VT-x * Package size: 37.5 mm × 37.5 mm * Steppings: B0 * TDP without FPGA. Total package TDP depends on functions included in FPGA. Max. TDP 7 W. * Temperature range: for (E625C, E645C, E665C): 0 °C to +70 °C, for (E625CT, E645CT, E665CT): -40 °C to +85 °C. * DDR2 single-channel memory controller supporting up to 2 GB * PCI Express 1.0a controller with 4 lanes * Display controller with LVDS and serial DVO ports * Integrated GMA600 (PowerVR) GPU * Integrated HD audio controller * Serial I/O supporting SPI


Silvermont microarchitecture


" Bay Trail-I" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, TXT/TXE * Package size: 25 mm × 27 mm * DDR3L dual-channel memory controller supporting up to 4 GB; ECC supported in single-channel mode * Display controller with 2 DDI ports (eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a) * Integrated Intel HD Graphics (Gen7) GPU * PCI Express 2.0 controller with four lanes and four root ports * Two SATA-300 ports * One USB 3.0 controller supporting one USB 3.0 port (can be multiplexed to support four USB 2.0 ports) * One USB 2.0 controller supporting four ports * Integrated LPE and HD audio controllers * Integrated image signal processor supporting three MIPI CSI ports, 24 MP sensors, and stereoscopic video * Integrated memory card reader supporting SDIO 3.0, eMMC 4.5, and SDXC * Serial I/O supporting SPI, UART (serial port), I2C or PWM


Airmont microarchitecture


" Braswell" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
. * GPU and memory controller are integrated onto the processor die * GPU is based on Broadwell Intel HD Graphics, with 12 execution units, and supports DirectX 11.2, OpenGL 4.3, OpenGL ES 3.0 and OpenCL 1.2 (on Windows). * Package size: 25 mm × 27 mm


Goldmont microarchitecture


" Apollo Lake" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x, Intel VT-d,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
, TXT/TXE * Package size: 24 mm × 31 mm * DDR3L/LPDDR3/LPDDR4 dual-channel memory controller supporting up to 8 GB; support for DDR3L with ECC * Display controller with 1 MIPI DSI port and 2 DDI ports (eDP 1.3, DP 1.1a, or HDMI 1.4b) * Integrated Intel HD Graphics (Gen9) GPU * PCI Express 2.0 controller supporting 6 lanes (3 dedicated and 3 multiplexed with USB 3.0); 4 lanes available externally * Two USB 3.0 ports (1 dual role, 1 dedicated, 3 multiplexed with PCI Express 2.0 and 1 multiplexed with one SATA-300 port) * Two USB 2.0 ports * Two SATA-600 ports (one multiplexed with USB 3.0) * Integrated HD audio controller * Integrated image signal processor supporting four MIPI CSI ports and 13 MP sensors * Integrated memory card reader supporting SDIO 3.01 and eMMC 5.0 * Serial I/O supporting SPI, HSUART (serial port) and I2C


Tremont microarchitecture


" Elkhart Lake" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x, Intel VT-d,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
. * GPU is based on Gen11 Intel HD Graphics, with up to 32 execution units, and supports up to 3 displays (4K @ 60 Hz) through
HDMI High-Definition Multimedia Interface (HDMI) is a proprietary digital interface used to transmit high-quality video and audio signals between devices. It is commonly used to connect devices such as televisions, computer monitors, projectors, gam ...
, DP, eDP, or DSI. * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0/3.0/3.1, 2 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, 3 × 2.5GbE LAN,
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and up to 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
3.0 in x4, x2, and x1 configurations. * Package size: 35 mm × 24 mm


Gracemont microarchitecture


"Amston Lake" (7 nm)

In Q2 2024 Intel launched these cpus: Atom® x7203C, Atom® x7211RE, Atom® x7213RE, Atom® x7405C, Atom® x7433RE, Atom® x7809C, Atom® x7835RE. These processors have 2-8 cpu cores and use 6-25 watts of power.


Server SoCs

All Atom server processors include ECC support.


Saltwell microarchitecture


" Centerton" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Hyper-threading, Intel 64, Intel VT-x,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct ''n''-bit data corruption which occurs in memory. Typically, ECC memory maintains a memory system immun ...
.


" Briarwood" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, Hyper-threading, Intel 64, Intel VT-x,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct ''n''-bit data corruption which occurs in memory. Typically, ECC memory maintains a memory system immun ...
.


Silvermont microarchitecture


" Avoton" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel Turbo Boost, Intel 64 (according to Datasheet), XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct ''n''-bit data corruption which occurs in memory. Typically, ECC memory maintains a memory system immun ...
. * Dual-core SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0, 2 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, 2 × Integrated GbE LAN, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and 4 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
2.0, in x4, x2, and x1 configurations. * Quad-core SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0, 2 (C2530) or 6 (C2550) ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, 2 × Integrated GbE LAN, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
2.0, in x8, x4, x2, and x1 configurations. * C2730 SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0, 2 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, 2 × Integrated GbE LAN, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and 8 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
2.0, in x8, x4, x2, and x1 configurations. * C2750 SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0, 6 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, 4 × Integrated GbE LAN, 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and 16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
2.0, in x16, x8, x4, x2, and x1 configurations. * Package size: 34 mm × 28 mm * Die size: 107 mm2


" Rangeley" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel Turbo Boost, Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct ''n''-bit data corruption which occurs in memory. Typically, ECC memory maintains a memory system immun ...
. * All models except C2x38 support ''Intel QuickAssist Technology'' (cryptography accelerator) * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0, 4-6 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
(1 for C2308, 2 for C2316, C2508, C2516), 4 × Integrated GbE LAN (2 for C2316), 2 ×
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and 8-16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
2.0 (4 lanes for C2308), in x16, x8, x4, x2, and x1 configurations. * Package size: 34 mm × 28 mm


Goldmont microarchitecture


" Denverton" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel Turbo Boost (dual-core, C3xx0, C3xx5 only), Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x, Intel VT-d,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct ''n''-bit data corruption which occurs in memory. Typically, ECC memory maintains a memory system immun ...
. * SoC peripherals include 8–16 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
3.0, 6–16 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, 4 × Integrated 1GbE, 2.5GbE, and 10GbE (C3538 and up) LAN, and up to 20 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
3.0, in x8, x4, and x2 configurations. * Package size: 34 mm × 28 mm


Tremont microarchitecture


" Snow Ridge" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct ''n''-bit data corruption which occurs in memory. Typically, ECC memory maintains a memory system immun ...
. * Same frequency for all models: 2.2 GHz. L2 cache: 4.5 MB per module; each module comprises four CPU cores. * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
3.0, 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0, 16 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, Integrated Intel Ethernet 800 series 100 Gbit/s LAN, 3 ×
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and up to 32 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
(16 × 2.0, 16 × 3.0), in x16, x8, and x4 configurations. * Intel Dynamic Load Balancer (Intel DLB) & Intel QuickAssist Technology (Intel QAT) * P####B models are designed for
base transceiver station A base transceiver station (BTS) or a baseband unit (BBU) is a piece of equipment that facilitates wireless communication between user equipment (UE) and a network. UEs are devices like mobile phone A mobile phone or cell phone is a portab ...
s, especially that for 5G networks. All other models are designed for communications (extended temperature range). * Package size: 47.5 mm × 47.5 mm


" Parker Ridge" (10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
, SSE4.1, SSE4.2, Intel 64, XD bit (an
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
implementation), Intel VT-x,
AES-NI An Advanced Encryption Standard instruction set (AES instruction set) is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern proces ...
,
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct ''n''-bit data corruption which occurs in memory. Typically, ECC memory maintains a memory system immun ...
. * SoC peripherals include 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
3.0, 4 ×
USB Universal Serial Bus (USB) is an industry standard, developed by USB Implementers Forum (USB-IF), for digital data transmission and power delivery between many types of electronics. It specifies the architecture, in particular the physical ...
2.0, 16 ×
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard ...
, Integrated Intel Ethernet 800 series 100 Gbit/s LAN (except 51xx model numbers), 3 ×
UART A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to ...
, and up to 32 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
(16 × 2.0, 16 × 3.0), in x16, x8, and x4 configurations. * Intel Dynamic Load Balancer (Intel DLB) & Intel QuickAssist Technology (Intel QAT) * Model numbers ending in 0 are extended temperature range; model numbers ending in 5 are commercial temperature range. * Package size: 47.5 mm × 47.5 mm


CE SoCs


Single-core CE SoCs


" Sodaville" (45 nm)

* Package size: 27 mm × 27 mm * GPU (based on the PowerVR SGX535 from Imagination Technologies)


" Groveland" (45 nm)

CE4200 * Package size: ?? mm × ?? mm * 2 × 32-bit memory channels, up to DDR2-800 * GPU (based on the PowerVR SGX535 from Imagination Technologies)


Dual-Core CE SoCs


" Berryville" (32 nm)

* Package size: ?? mm × ?? mm * GPU for 3D (based on the PowerVR SGX545 from Imagination Technologies) * GPU for 2D
GC300
from
Vivante Vivante Corporation was a Fabless manufacturing, fabless semiconductor industry, semiconductor company headquartered in Sunnyvale, California, with an R&D center in Shanghai, China. The company was founded in 2004 as GiQuila and focused on the ...
)


See also

* Atom (system on chip) * Comparison of Intel processors * List of Intel Celeron microprocessors *
Intel GMA The Intel Graphics Media Accelerator (GMA) is a series of integrated graphics processors introduced in 2004 by Intel, replacing the earlier Intel Extreme Graphics series and being succeeded by the Intel HD and Iris Graphics series. This serie ...
* Stealey (A100/A110) *
Geode (processor) Geode is a series of x86-compatible system-on-a-chip (SoC) microprocessors and I/O companions produced by AMD that was targeted at the Embedded system, embedded computing market. The series was originally launched by National Semiconductor as t ...
* VIA Nano * Intel Quark * Intel Edison


References


External links


Intel Atom Processor - Overview

SSPEC/QDF Reference
(Intel)
Intel Corporation - Processor Price List

Intel Atom and VIA Nano performance compared




{{DEFAULTSORT:Intel Atom Microprocessors *Atom Lists of microprocessors