|
Intel Communication Streaming Architecture
Intel's Communication Streaming Architecture (CSA) was a mechanism used in the Intel Hub Architecture to increase the bandwidth available between a network card and the CPU. It consists of connecting directly the network controller to the Memory Controller Hub (northbridge (computing), northbridge), instead of to the I/O Controller Hub (southbridge) through the Conventional PCI, PCI bus, which was the common practice until that point. The technology was only used in Intel chipsets released in 2003, and was largely seen as a stop-gap measure to allow Gigabit Ethernet chips to run at full-speed until the arrival of a faster expansion bus (it was also used to connect the Wireless networking chips in Intel's Centrino mobile platform). To Intel's credit though, CSA-connected Ethernet chips did show consistently higher transfer rates than comparable PCI cards. The following year, PCI Express replaced CSA as the method of connecting network chips in Intel's chipsets, and the technology ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel Hub Architecture
Intel Hub Architecture (IHA), also known as Accelerated Hub Architecture (AHA) was Intel's architecture for the 8xx family of chipsets, starting in 1999 with the Intel 810. It uses a memory controller hub (MCH) that is connected to an I/O controller hub (ICH) via a 266 MB/s bus. The MCH chip supports memory and AGP (replaced by PCI Express in 9xx series chipsets), while the ICH chip provides connectivity for PCI (revision 2.2 before ICH5 series and revision 2.3 since ICH5 series), USB (version 1.1 before ICH4 series and version 2.0 since ICH4 series), sound (originally AC'97, Azalia added in ICH6 series), IDE hard disks (supplemented by Serial ATA since ICH5 series, fully replaced IDE since ICH8 series for desktops and ICH9 series for notebooks) and LAN (uncommonly activated on desktop motherboards and notebooks, usually independent LAN controller were placed instead of PHY chip). Intel claimed that, because of the high-speed channel between the sections, the IHA was faster tha ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Memory Controller Hub
In computing, a northbridge (also host bridge, or memory controller hub) is one of two chips comprising the core logic chipset architecture on a PC motherboard. A northbridge is connected directly to a CPU via the front-side bus (FSB) to handle high-performance tasks, and is usually used in conjunction with a slower southbridge to manage communication between the CPU and other parts of the motherboard. Since the 2010s, die shrink and improved transistor density have allowed for increasing chipset integration, and the functions performed by northbridges are now often incorporated into other components (like southbridges or CPUs themselves). As of 2019, Intel and AMD had both released chipsets in which all northbridge functions had been integrated into the CPU. Modern Intel Core processors have the northbridge integrated on the CPU die, where it is known as the uncore or system agent. On older Intel based PCs, the northbridge was also named external memory controller hub ( ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Northbridge (computing)
In computing, a northbridge (also host bridge, or memory controller hub) is one of two chips comprising the core logic chipset architecture on a PC motherboard. A northbridge is connected directly to a CPU via the front-side bus (FSB) to handle high-performance tasks, and is usually used in conjunction with a slower southbridge to manage communication between the CPU and other parts of the motherboard. Since the 2010s, die shrink and improved transistor density have allowed for increasing chipset integration, and the functions performed by northbridges are now often incorporated into other components (like southbridges or CPUs themselves). As of 2019, Intel and AMD had both released chipsets in which all northbridge functions had been integrated into the CPU. Modern Intel Core processors have the northbridge integrated on the CPU die, where it is known as the uncore or system agent. On older Intel based PCs, the northbridge was also named external memory controller hub (''MC ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
I/O Controller Hub
I/O Controller Hub (ICH) is a family of Intel southbridge microchips used to manage data communications between a CPU and a motherboard, specifically Intel chipsets based on the Intel Hub Architecture. It is designed to be paired with a second support chip known as a northbridge. As with any other southbridge, the ICH is used to connect and control peripheral devices. As CPU speeds increased data transmission between the CPU and support chipset, the support chipset eventually emerged as a bottleneck between the processor and the motherboard. Accordingly, starting with the Intel 5 Series, a new architecture was used that incorporated some functions of the traditional north and south bridge chips onto the CPU itself, with the remaining functions being consolidated into a single Platform Controller Hub (PCH). This replaces the traditional two chip setup. ICH The first version of the ICH was released in June 1999 along with the Intel 810 northbridge. While its predecessor, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Conventional PCI
Peripheral Component Interconnect (PCI) is a local computer bus for attaching hardware devices in a computer and is part of the PCI Local Bus standard. The PCI bus supports the functions found on a processor bus but in a standardized format that is independent of any given processor's native bus. Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in the processor's address space. It is a parallel bus, synchronous to a single bus clock. Attached devices can take either the form of an integrated circuit fitted onto the motherboard (called a ''planar device'' in the PCI specification) or an expansion card that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatibles, where it displaced the combination of several slow Industry Standard Architecture (ISA) slots and one fast VESA Local Bus (VLB) slot as the bus configuration. It has subsequently been adopted for other computer types ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Gigabit Ethernet
In computer networking, Gigabit Ethernet (GbE or 1 GigE) is the term applied to transmitting Ethernet frames at a rate of a gigabit per second. The most popular variant, 1000BASE-T, is defined by the IEEE 802.3ab standard. It came into use in 1999, and has replaced Fast Ethernet in wired local networks due to its considerable speed improvement over Fast Ethernet, as well as its use of cables and equipment that are widely available, economical, and similar to previous standards. History Ethernet was the result of research conducted at Xerox PARC in the early 1970s, and later evolved into a widely implemented physical and link layer protocol. Fast Ethernet increased the speed from 10 to 100 megabits per second (Mbit/s). Gigabit Ethernet was the next iteration, increasing the speed to 1000 Mbit/s. * The initial standard for Gigabit Ethernet was produced by the IEEE in June 1998 as IEEE 802.3z, and required optical fiber. 802.3z is commonly referred to as 1000BASE-X, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Wireless Networking
A wireless network is a computer network that uses wireless data connections between network nodes. Wireless networking is a method by which homes, telecommunications networks and business installations avoid the costly process of introducing cables into a building, or as a connection between various equipment locations. Admin telecommunications networks are generally implemented and administered using radio communication. This implementation takes place at the physical level (layer) of the OSI model network structure. Examples of wireless networks include cell phone networks, wireless local area networks (WLANs), wireless sensor networks, satellite communication networks, and terrestrial microwave networks. History Wireless networks The first professional wireless network was developed under the brand ALOHAnet in 1969 at the University of Hawaii and became operational in June 1971. The first commercial wireless network was the WaveLAN product family, developed by NC ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Centrino
Centrino is a brand name of Intel Corporation which represents its Wi-Fi and WiMAX wireless computer networking adapters. Previously the same brand name was used by the company as a platform-marketing initiative. The change of the meaning of the brand name occurred on January 7, 2010. The Centrino was replaced by the Ultrabook. The old platform-marketing brand name covered a particular combination of mainboard chipset, mobile CPU and wireless network interface in the design of a laptop. Intel claimed that systems equipped with these technologies delivered better performance, longer battery life and broader wireless network interoperability than non-Centrino systems. The new product line name for Intel wireless products is Intel Centrino Wireless. Intel Centrino Notebook implementations Carmel platform (2003) Intel used " Carmel" as the codename for the first-generation Centrino platform, introduced in March 2003. Industry-watchers initially criticized the Carmel p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers' graphics cards, hard disk drive host adapters, SSDs, Wi-Fi and Ethernet hardware connections. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER), and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization. The PCI Express electrical interface is measured by the number of simultaneous lanes. (A lane is a single send/receive line of data. The analogy is a highway with traffic in both direc ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
