Dynamic random-access memory

Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-accesssemiconductor memory that stores each bit of data in a memory cell. A DRAM memory cell usually consists of a microscopic capacitor and a transistor, both typically based on metal–oxide–semiconductor (MOS) technology.

While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors gradually leaks away; without intervention, the data on the capacitor would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory (as opposed to non-volatile memory), since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.

DRAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in digital electronics where low-cost, high-capacity computer memory is required. One of the largest applications for DRAM is the main memory (colloquially called the RAM) in modern computers and graphics cards (where the main memory is called the graphics memory). It is also used in many portable devices and video game consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.

The need to refresh DRAM demands more complicated circuitry and timing than SRAM. This complexity is offset by the structural simplicity of DRAM memory cells: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities with a simultaneous reduction in cost per bit. Refreshing the data consumes power, causing a variety of techniques to be used to manage the overall power consumption. For this reason, DRAM usually needs to operate with a memory controller; the memory controller needs to know DRAM parameters, especially memory timings, to initialize DRAMs, which may be different depending on different DRAM manufacturers and part numbers.

In 2017, DRAM had a 47% increase in the price-per-bit, the largest jump in 30 years since a 45% jump in 1988. In 2018, a "key characteristic of the DRAM market" was that there were "only three major suppliers — Micron Technology, SK Hynix and Samsung Electronics" that were "keeping a pretty tight rein on their capacity". In early 2026, DRAM (DDR4, DDR, and flash memory/NAND) prices have "experienced compounded increases, some exceeding 200%, since early 2025 .. [because of] unprecedented demand coming from the AI sector .. HBM is crowding out commodity DRAM capacity. Micron noted a 3-to-1 conversion ratio between HBM and DDR5 wafer capacity, meaning every HBM ramp directly compresses general-purpose memory supply."

Other manufacturers make and sell DIMMs but not the DRAM chips in them, such as Kingston Technology, and some manufacturers sell stacked DRAM (used e.g. in the fastest supercomputers on the exascale) separately such as . Others sell such integrated into other products, such as Fujitsu into its CPUs, AMD in GPUs, and Nvidia, with HBM2 in some of their GPU chips.