Nios II is a

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embedded processor architecture designed specifically for the

Altera Altera Corporation is a manufacturer of programmable logic devices (PLDs) headquartered in San Jose, California. It was founded in 1983 and acquired by Intel in 2015 before becoming independent once again in 2025 as a company focused on developm ...

family of field-programmable gate array (FPGA)

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. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from

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(DSP) to system-control. Nios II is a successor to Altera's first configurable

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embedded processor Nios, introduced in 2000. Intel announced the discontinuation of Nios II in 2023, with its successor being

Nios V Nios or NIOS may refer to: Places * Ios or Nios, a Greek island Computing * Network I/O System, Digital Research's NIOS component in CP/NET in the 1980s * NetWare I/O Subsystem, Novell's NIOS component in the 32-bit network clients in the mid ...

, based on the

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architecture.

Key features

Like the original Nios, the Nios II architecture is a

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architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full

design: * 32 general-purpose 32-bit registers, * Full 32-bit instruction set, data path, and address space, * Single-instruction 32 × 32 multiply and divide producing a 32-bit result. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by, for example, adding a predefined memory management unit, or defining custom instructions and custom peripherals.

Custom instructions

Similar to native Nios II instructions, user-defined instructions accept values from up to two 32-

bit The bit is the most basic unit of information in computing and digital communication. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represented as ...

source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in C.

Custom peripherals

For performance-critical systems that spend most CPU cycles executing a specific section of code, a user-defined peripheral can potentially offload part or all of the execution of a software-algorithm to user-defined hardware logic, improving power-efficiency or application throughput.

Memory Management Unit

Introduced with

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8.0, the optional MMU enables Nios II to run operating systems which require hardware-based paging and protection, such as the Linux kernel. Without an MMU, Nios is restricted to operating systems which use a simplified protection and virtual memory-model: e.g.,

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and

FreeRTOS FreeRTOS is a real-time operating system Kernel (operating system), kernel for embedded devices that has been ported to 40 microcontroller platforms. It is distributed under the MIT License. History The FreeRTOS kernel was originally developed ...

Memory Protection Unit

Introduced with Quartus 8.0, the optional MPU provides memory protection similar to that provided by an MMU but with a simpler programming model and without the performance overhead associated with an MMU.

Nios II CPU family

Nios II classic is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). Nios II gen2 is offered in 2 different configurations: Nios II/f (fast), and Nios II/e (economy).

Nios II/f

The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include: * Separate instruction and data caches (512 B to 64 KB) * Optional

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or MPU * Access to up to 2 GB of external address space * Optional tightly coupled memory for instructions and data * Six-stage pipeline to achieve maximum

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/MHz * Single-cycle hardware multiply and barrel shifter * Optional hardware divide option * Dynamic

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* Up to 256 custom instructions and unlimited hardware accelerators *

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debug module * Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

Nios II/s

Nios II/s core is designed to maintain a balance between performance and cost. This core implementation is not longer supported for Altera Quartus II v.17 and newer. Features of Nios II/s include: * Instruction cache * Up to 2 GB of external address space * Optional tightly coupled memory for instructions * Five-stage pipeline * Static branch prediction * Hardware multiply, divide, and shift options * Up to 256 custom instructions *

debug module * Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

Nios II/e

The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include: * Up to 2 GB of external address space *

debug module * Complete systems in fewer than 700 LEs * Optional debug enhancements * Up to 256 custom instructions * Free, no license required

Avalon switch fabric interface

Nios II uses the Avalon switch fabric as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave-side arbitration scheme, lets multiple masters operate simultaneously.

Development processes

Development for Nios II consists of two separate steps: hardware generation and software creation. Development is hosted inside an Altera application called the Embedded Design Suite (EDS). The EDS contains a complete integrated development environment to manage both hardware and software in two separate steps:

Hardware generation process

Nios II hardware designers use the Qsys system integration tool, a component of the Quartus-II package, to configure and generate a Nios system. The configuration

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(GUI) allows users to choose the Nios-II's feature-set, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus-II performs the synthesis, place & route to implement the entire system on the selected FPGA target.
Qsys is replacing the older SOPC (System-on-a-Programmable-Chip) Builder, which could also be used to build a Nios II system, and is being recommended for new projects.

Software creation process

A separate package, called the Embedded Design Suite (EDS), manages the software development. Based on the

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IDE, the EDS includes a C/C++ compiler (based on the

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), debugger, and an instruction-set simulator. EDS allows programmers to test their application in simulation, or download and run their compiled application on the actual FPGA host. Because the C/C++ development-chain is based on

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, the vast majority of

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software for

Linux Linux ( ) is a family of open source Unix-like operating systems based on the Linux kernel, an kernel (operating system), operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically package manager, pac ...

compiles and runs with minimal or no modification. Third-party operating-systems have also been ported to Nios II. These include Micrium

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eCos The Embedded Configurable Operating System (eCos) is a free and open-source real-time operating system intended for embedded systems and applications which need only one process with multiple threads. It is designed to be customizable to preci ...

, Segger Microcontroller embOS, ChibiOS/RT,

μCLinux μClinux is a variation of the Linux kernel, previously maintained as a fork, that targets microcontrollers without a memory management unit (MMU). It was integrated into the mainline kernel as of 2.5.46; the project continues to develop patc ...

and

. GCC 15 removed support for Nios II processors due to Nios II's discontinuation.

Licensing

Nios II is comparable to MicroBlaze, a competing softcore CPU for the

Xilinx Xilinx, Inc. ( ) was an American technology and semiconductor company that primarily supplied programmable logic devices. The company is renowned for inventing the first commercially viable field-programmable gate array (FPGA). It also pioneered ...

family of FPGA. Unlike MicroBlaze, Nios II is licensable for standard-cell

ASIC An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficien ...

s through a third-party IP provider,

Synopsys Synopsys, Inc. is an American electronic design automation (EDA) company headquartered in Sunnyvale, California, that focuses on silicon design and verification, silicon intellectual property and software security and quality. Synopsys sup ...

Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.

References

External links

Intel's site about Nios IINios II Embedded Design Suite forumNios community wiki
*

RTEMS Real-Time Executive for Multiprocessor Systems (RTEMS), formerly Real-Time Executive for Missile Systems, and then Real-Time Executive for Military Systems, is a real-time operating system (RTOS) designed for embedded systems. It is free and open ...

real-time operating system
Cornell ECE576 Microcontroller course using NiosIIUPB ECE31289 course using Nios II
{{DEFAULTSORT:Nios Ii Soft microprocessors