Write combining (WC) is a
computer bus
In computer architecture, a bus (shortened form of the Latin '' omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This ex ...
technique for allowing
data to be combined and temporarily stored in a
buffer the write combine buffer (WCB) to be released together later in
burst mode instead of writing (immediately) as single
bits or small chunks.
Technique
Write combining cannot be used for general memory access (data or code regions) due to the
weak ordering. Write-combining does not guarantee that the combination of writes and reads is done in the expected order. For example, a
write/
read/
write combination to a specific address would lead to the write combining order of
read/
write/
write which can lead to obtaining wrong values with the first read (which potentially relies on the write before).
In order to avoid the problem of read/write order described above, the
write buffer
A write buffer is a type of data buffer that can be used to hold data being written from the cache to main memory or to the next cache in the memory hierarchy to improve performance and reduce latency. It is used in certain CPU cache architectu ...
can be treated as a
fully associative
A CPU cache is a memory which holds the recently utilized data by the processor. A block of memory cannot necessarily be placed randomly in the cache and may be restricted to a single CPU cache#Cache entries, cache line or a set of cache lines by ...
cache and added into the
memory hierarchy
In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time. Since response time, complexity, and capacity are related, the levels may also be distinguished by their performance and controlli ...
of the device in which it is implemented.
Adding complexity slows down the
memory hierarchy
In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time. Since response time, complexity, and capacity are related, the levels may also be distinguished by their performance and controlli ...
so this technique is often only used for memory which does not need
strong ordering
Strong may refer to:
Education
* The Strong, an educational institution in Rochester, New York, United States
* Strong Hall (Lawrence, Kansas), an administrative hall of the University of Kansas
* Strong School, New Haven, Connecticut, United St ...
(always correct) like the
frame buffers of
video cards.
See also
*
Framebuffer (FB), and when linear: LFB
*
Memory type range registers (MTRR) – the older x86 cache control mechanism
*
Page attribute table (PAT) – x86 page table extension that allows fine-grained cache control, including write combining
*
Page table
*
Uncacheable speculative write combining Uncacheable speculative write combining (USWC), is a computer BIOS setting for memory communication between a CPU and graphics card. It allows faster communication than the "uncachable" setting (the alternative to USWC in the BIOS), as long as t ...
(USWC)
*
Video Graphics Array (VGA), and Banked (BVGA) Frame Buffer
References
{{Reflist
External links
6x86opt, ctppro, CTU, DirectNT, FastVid, fstorion, K6Speed, MTRRLFBE, S3 Speed Up & Write Allocate Monitorenable
LFB and BVGA Write Combining on Intel Pentium Pro/2/3/4 and AMD K6
CPU
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and ...
s in Windows 9x, Windows NTx, DOS, OS/2 and Linux
MTRRLFBEenable LFB and BVGA Write Combining on Intel Pentium Pro/2/3/4 CPUs in Windows 9x and DOS
CTU(Internet Archive cached copy) enable LFB and Banked VGA Write Combining on AMD K6 CPUs in Windows 9x and DOS
Computer buses
Computer memory