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Universal Chiplet Interconnect Express (UCIe) is an
open specification An open standard is a standard that is openly accessible and usable by anyone. It is also a common prerequisite that open standards use an open license that provides for extensibility. Typically, anybody can participate in their development due to ...
for a die-to-die
interconnect In telecommunications, interconnection is the physical linking of a carrier's network with equipment or facilities not belonging to that network. The term may refer to a connection between a carrier's facilities and the equipment belonging to its ...
and
serial bus In telecommunication and data transmission, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits ar ...
between
chiplet A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package to create a complex component such as a computer processor. E ...
s. It is co-developed by
AMD Advanced Micro Devices, Inc. (AMD) is an American multinational corporation and technology company headquartered in Santa Clara, California and maintains significant operations in Austin, Texas. AMD is a hardware and fabless company that de ...
,
Arm In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between ...
, ASE Group,
Google Cloud Google Cloud Platform (GCP) is a suite of cloud computing services offered by Google that provides a series of modular cloud services including computing, data storage, data analytics, and machine learning, alongside a set of management tools ...
,
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
,
Meta Meta most commonly refers to: * Meta (prefix), a common affix and word in English ( in Greek) * Meta Platforms, an American multinational technology conglomerate (formerly ''Facebook, Inc.'') Meta or META may also refer to: Businesses * Meta (ac ...
,
Microsoft Microsoft Corporation is an American multinational corporation and technology company, technology conglomerate headquartered in Redmond, Washington. Founded in 1975, the company became influential in the History of personal computers#The ear ...
,
Qualcomm Qualcomm Incorporated () is an American multinational corporation headquartered in San Diego, California, and Delaware General Corporation Law, incorporated in Delaware. It creates semiconductors, software and services related to wireless techn ...
,
Samsung Samsung Group (; stylised as SΛMSUNG) is a South Korean Multinational corporation, multinational manufacturing Conglomerate (company), conglomerate headquartered in the Samsung Town office complex in Seoul. The group consists of numerous a ...
, and
TSMC Taiwan Semiconductor Manufacturing Company Limited (TSMC or Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is one of the world's most valuable semiconductor companies, the world' ...
. In August 2022,
Alibaba Group Alibaba Group Holding Limited, branded as Alibaba (), is a Chinese Multinational corporation, multinational technology company specializing in E-commerce in China, e-commerce, retail, Internet, and technology. Founded on 28 June 1999 in Hangzho ...
and
Nvidia Nvidia Corporation ( ) is an American multinational corporation and technology company headquartered in Santa Clara, California, and incorporated in Delaware. Founded in 1993 by Jensen Huang (president and CEO), Chris Malachowsky, and Curti ...
joined as board members.


Overview

A common chiplet interconnect specification enables construction of large
System-on-Chip A system on a chip (SoC) is an integrated circuit that combines most or all key components of a computer or electronic system onto a single microchip. Typically, an SoC includes a central processing unit (CPU) with memory, input/output, and da ...
(SoC) packages that exceed maximum
reticle A reticle or reticule, also known as a graticule or crosshair, is a pattern of fine lines or markings built into the eyepiece of an optical device such as a telescopic sight, spotting scope, theodolite, optical microscope or the electronic v ...
size. It allows intermixing components from different silicon vendors within the same package and improves manufacturing yields by using smaller dies. Each chiplet can use a different silicon manufacturing process, suitable for a specific device type, or computing performance and power draw requirements.


Specifications


1.0

The UCIe 1.0 specification was released on March 2, 2022. It defines
physical layer In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer: the layer most closely associated with the physical connection between devices. The physical layer provides an electrical, mechani ...
, protocol stack and software model, as well as procedures for compliance testing. The physical layer supports up to 32
GT/s In computer technology, transfers per second and its more common secondary terms gigatransfers per second (abbreviated as GT/s) and megatransfers per second (MT/s) are informal language that refer to the number of operations transferring data that ...
with 16 to 64 lanes and uses a 256 byte Flow Control Unit (FLIT) for data, similar to
PCIe PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as Peripher ...
6.0; the protocol layer is based on
Compute Express Link Compute Express Link (CXL) is an open standard interconnect for high-speed, high capacity CPU-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the serial PCI Express (PCIe) physical ...
with CXL.io (PCIe), CXL.mem and CXL.cache protocols. Various on-die interconnect technologies are defined, like organic substrate for a 'standard' 2D package, or embedded silicon bridge (EMIB), silicon interposer, and fanout embedded bridge for 'advanced' 2.5D/3D packages. Physical specifications are based on Intel's Advanced Interface Bus (AIB). Shorter signal paths allow the links to have 20× better I/O performance and power consumption (~0.5 p J per bit) comparing to typical PCIe
SerDes A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The ter ...
, with bandwidth density up to 1.35 TB/s per mm2 for a common bump pitch of 45 
μm The micrometre (Commonwealth English as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer (American English), also commonly known by the non-SI term micron, is a unit of length in the International System ...
, and 3.24× higher density with a bump pitch of 25 Î¼m. Future versions may include additional protocols, wider data links, and higher density connections.


1.1

The UCIe 1.1 specification was released on August 8, 2023. Highlights: * Architectural Specification Enhancements enable compliance testing * Supports simultaneous multiprotocol with full link layer functionality for streaming protocols * Includes runtime health monitoring and repair for automotive and high-reliability applications * New bump maps result in lower cost packaging


2.0

The UCIe 2.0 specification was released on August 6, 2024. Highlights: * Holistic support for manageability, debug, and testing for any System-in-Package (SiP) construction with multiple chiplets. * Support for 3D packaging to significantly enhance bandwidth density and power efficiency. * Improved system-level solutions with manageability defined as part of the chiplet stack. * Optimized package designs for interoperability and compliance testing. * Fully backward compatible with UCIe 1.x


References


External links

* {{Official website, https://www.uciexpress.org/ Computer-related introductions in 2022 Open standards Serial buses Peripheral Component Interconnect