Transaction Verification Model

A Bus Functional Model (BFM; also known as a Transaction Verification Model or TVM) is a non- synthesizable software model of an integrated circuit component having one or more external buses. The emphasis of the model is on simulating system bus transactions prior to building and testing the actual hardware. BFMs are usually defined as tasks in Hardware description languages (HDLs), which apply stimuli to the design under verification via complex waveforms and protocols. A BFM is typically implemented using hardware description languages such as Verilog, VHDL, SystemC, or SystemVerilog.

Typically, BFMs offer a two-sided interface: One interface side drives and samples low-level signals according to the bus protocol. On its other side, tasks are available to create and respond to bus transactions. BFMs are often used as reusable building blocks to create simulation test benches, in which the bus interface ports of a design under test are connected to appropriate BFMs.

Another common application of BFMs is the provision of substitute models for IP components: Instead of a netlist or RTL design of an IP component, a 3rd party IP supplier might provide only a BFM suitable for verification purposes. The actual IP component in the form of a gate-level netlist can be directly provided to the foundry by the IP provider.

In the past, BFM were treated as a non-synthesizable entity, however recently BFMs are becoming available as synthesizable models as well.

Transaction Verification Models

BFMs are sometimes referred to as TVMs or Transaction Verification Models. This is to emphasize that bus operations of the model have been bundled into atomic bus transactions to make it easier to issue and view bus transactions. Visualizations of the bus transactions modeled by TVMs are similar to the output of a protocol analyzer or bus sniffer.

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Logic design

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