Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.

History

SSSE3 was first introduced with Intel processors based on the Core microarchitecture on June 26, 2006 with the "Woodcrest" Xeons. SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it. SSSE3 has enhanced for HD audio/video decoding/encoding, for example AAC.

Functionality

SSSE3 contains 16 new discrete instructions. Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. They include: * Twelve instructions that perform horizontal addition or subtraction operations. * Six instructions that evaluate absolute values. * Two instructions that perform multiply-and-add operations and speed up the evaluation of

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s. * Two instructions that accelerate packed integer multiply operations and produce integer values with scaling. * Two instructions that perform a byte-wise, in-place shuffle according to the second shuffle control operand. * Six instructions that negate packed integers in the destination operand if the corresponding element in the source operand is negative. * Two instructions that align data from the composite of two operands.

CPUs with SSSE3

* AMD: ** "Cat" low-power processors *** Bobcat-based processors *** Jaguar-based processors and newer *** Puma-based processors and newer ** "Heavy Equipment" processors *** Bulldozer-based processors *** Piledriver-based processors *** Steamroller-based processors *** Excavator-based processors and newer ** Zen-based processors ** Zen+-based processors ** Zen2-based processors ** Zen3-based processors ** Zen4-based processors ** Zen5-based processors * Intel: ** Xeon 5100 Series ** Xeon 5300 Series ** Xeon 5400 Series ** Xeon 3000 Series ** Core 2 Duo ** Core 2 Extreme ** Core 2 Quad ** Core i7 ** Core i5 ** Core i3 ** Pentium Dual Core (if 64-bit capable; Allendale onwards) ** Celeron 4xx Sequence Conroe-L ** Celeron Dual Core E1200 ** Celeron M 500 series **

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* VIA: ** Nano

New instructions

In the table below, (read as 'saturate to signed word') takes a signed integer X, and converts it to −32768 if it is less than −32768, to +32767 if it is greater than 32767, and leaves it unchanged otherwise. As normal for the Intel architecture, bytes are 8 bits, words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMM vector register.

References

External links

Core 2 Mobile specificationsIntel white-paper admitting the existence of SSSE3 and describing SSE4Instruction set documentation listing the functions of the SSSE3 instructions
{{DEFAULTSORT:Ssse3 X86 instructions SIMD computing