R4200

The R4200 is a microprocessor designed by MIPS Technologies that implemented the MIPS III instruction set architecture and was initially referred to as the VRX during development. MIPS, which had no production capability of its own, licensed the design to NEC, which fabricated and marketed it as the VR4200. The first VR4200, running at 80 MHz, was introduced in 1993, with a faster 100 MHz version following in 1994.

Primarily aimed at low-power Windows NT systems such as personal computers and laptops, the R4200 was marketed as offering "Pentium processor performance at a tenth of the price." It was initially expected to deliver twice the performance of a 66 MHz Intel 486DX2 processor. SPECint benchmark results showed the microprocessor’s integer performance at approximately 85% of the original Pentium, while its floating-point performance was about half that of the Pentium.

The R4300i is a derivative of the R4200, designed by MIPS for embedded applications. A variant of the R4300i was used in the widely popular Nintendo 64 and SNK's Hyper Neo Geo 64 arcade board.

The R4200 never saw use in personal computers and was eventually repositioned as an embedded microprocessor complementing the R4600.

Description

The R4200 is a scalar design with a five-stage classic RISC pipeline. A notable feature is the use of two datapaths for performing floating point arithmetic (using the integer datapath for the mantissa, and a separate datapath for the exponent). This scheme reduced chip size and transistor count, reducing cost and power consumption. Whilst this reduced floating point performance, the R4200's intended applications did not require high floating point performance.

The R4200 has a 16  kB instruction cache and an 8 kB data cache. Both caches are direct-mapped. The instruction cache has a 32-byte line size, whereas the data cache has 16-byte line size. The data cache uses the write-back write protocol.

The R4200 has a 32-entry translation lookaside buffer (TLB) for data, and a 4-entry TLB for instructions. A 33-bit physical address is supported. The system bus is 64 bits wide and operates at half the internal clock frequency.

The R4200 contained 1.3 million transistors and had an area of 81 mm². NEC fabricated the R4200 in a 600 nm process with three levels of interconnect. It was packaged in a 179-pin ceramic pin grid array that was compatible with the R4x00PC and R4600, or a 208-pin plastic quad flat pack (PQFP). It used a 3.3 V power supply, dissipating 1.8 W typically and a maximum of 2 W at 80 MHz.

In comparison to the Pentium, SPECint ratings had the Pentium at 64.5 and the R4200 at 55. SPECfp ratings had the Pentium at 56 versus the R4200 at 30.

R4300i

The R4300i is a derivative of the R4200, designed by MIPS for embedded applications and announced on 17 April 1995. It improves on the R4200 with a faster integer multiplier featuring lower latency and a simplified 32-bit system bus to reduce costs. The chip, measuring 45 mm², was fabricated using a 350 nm process and was packaged in a low-cost 120-pin PQFP by employing multiplexed address and data lines. It operates on a 3.3 V power supply and dissipating 1.5 W at 40 MHz (80 MHz internally), 1.8 W at 100 MHz and 2.2 W at 133 MHz.

The R4300i was licensed to NEC and Toshiba, who marketed it as the VR4300 and TX4300, respectively, with 100 and 133 MHz versions.

NEC produced a version of the VR4300 for the Nintendo 64 called the CPU-NUS, clocked at 93.75 MHz with a performance of 125 million instructions per second. ''Popular Electronics'' compared its processing power to that of contemporary Pentium desktop processors. Though constrained by a narrower 32-bit system bus, the VR4300 retained the computational capabilities of the more powerful 64-bit R4300i. However, software rarely utilized 64-bit precision, as Nintendo 64 games primarily relied on faster and more compact 32-bit operations.

NEC also developed two other derivatives for the embedded market, the VR4305 and VR4310, announced on 20 January 1998. The VR4310, available at 100, 133, or 167 MHz, was manufactured in a 250 nm process and packaged in a 120-pin PQFP.

References

* "MIPS, NEC will launch 64-bit device". (17 April 1995). ''Electronic News''.
* "NEC Unveils New MIPS Chip for Nintendo". (8 May 1995). ''Microprocessor Report''.
* Gwennap, Linley (31 May 1993). "MIPS Reaches New Lows With R4200 Design". ''Microprocessor Report'', pp. 6–9.
* Levy, Marcus (15 September 1994). "EDN's 21st Annual Microprocessor Directory". '' EDN''.
* Ryan, Bob; Thompson, Tom (January 1994). "RISC Grows Up". ''Byte''.
* Yeung, N.K. et al. (1994). "The design of a 55SPECint92 RISC processor under 2W". ''ISSCC Digest of Technical Papers''. pp. 206–207.
* Zivkov, B.; Ferguson, B.; Gupta, M. (1994). ''Compcon Spring '94, Digest of Papers''. pp. 18–25.

{{NEC Corporation

MIPS implementations
MIPS microprocessors
NEC microprocessors
64-bit microprocessors