Quad Data Rate (QDR) SRAM is a type of

static RAM Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed. The term ''static'' differe ...

computer memory In computing, memory is a device or system that is used to store information for immediate use in a computer or related computer hardware and digital electronic devices. The term ''memory'' is often synonymous with the term '' primary storage ...

that can transfer up to four words of

data In the pursuit of knowledge, data (; ) is a collection of discrete values that convey information, describing quantity, quality, fact, statistics, other basic units of meaning, or simply sequences of symbols that may be further interpret ...

in each

clock A clock or a timepiece is a device used to measure and indicate time. The clock is one of the oldest human inventions, meeting the need to measure intervals of time shorter than the natural units such as the day, the lunar month and t ...

cycle. Like Double Data-Rate (DDR) SDRAM, QDR SRAM transfers data on both rising and falling edges of the clock signal. The main purpose of this capability is to enable reads and writes to occur at high clock frequencies without the loss of bandwidth due to bus-turnaround cycles incurred in DDR SRAM. QDR SRAM uses two clocks, one for read data and one for write data and has separate read and write data buses (also known as Separate I/O), whereas DDR SRAM uses a single clock and has a single common data bus used for both reads and writes (also known as Common I/O). This helps to eliminate problems caused by the propagation delay of the clock wiring, and allows the illusion of concurrent reads and writes (as seen on the bus, although internally the memory still has a conventional single port - operations are pipelined but sequential). When all data I/O signals are accounted, QDR SRAM is not 2x faster than DDR SRAM but is 100% efficient when reads and writes are interleaved. In contrast, DDR SRAM is most efficient when only one request type is continually repeated, e.g. only read cycles. When write cycles are interleaved with read cycles, one or more cycles are lost for bus turnaround to avoid data contention, which reduces bus efficiency. Most SRAM manufacturers constructed QDR and DDR SRAM using the same physical silicon, differentiated by a post-manufacturing selection (e.g. blowing a fuse on chip).{{citation needed, date=June 2021 QDR SRAM was designed for high-speed

communication Communication (from la, communicare, meaning "to share" or "to be in relation with") is usually defined as the transmission of information. The term may also refer to the message communicated through such transmissions or the field of inqu ...

s and networking applications, where data throughput is more important than cost, power efficiency or density. The technology was created by

Micron The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer ( American spelling), also commonly known as a micron, is a unit of length in the International System of Un ...

and

Cypress Cypress is a common name for various coniferous trees or shrubs of northern temperate regions that belong to the family Cupressaceae. The word ''cypress'' is derived from Old French ''cipres'', which was imported from Latin ''cypressus'', the la ...

, later followed by IDT, then NEC,

Samsung The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...

and

Renesas is a Japanese semiconductor manufacturer headquartered in Tokyo, Japan, initially incorporated in 2002 as Renesas Technology, the consolidated entity of the semiconductor units of Hitachi and Mitsubishi excluding their dynamic random-access mem ...

. Quad Data Rate II+ Memory is currently being designed by Cypress Semiconductor for Radiation Hardened Environments.

I/O

Clock inputs

4 clock lines: * Input clock: ** K ** not-K, or /K * Output clock: ** C ** not-C, or /C

Control inputs

Two control lines: *not-Write enable: /WPS *not-Read enable: /RPS

Buses

One address bus and two data buses: *Address bus *Data in bus *Data out bus

Clocking scheme

*Addresses **Read address latched on rising edge of C **Write address latched on rising edge of K (in burst-of-4 mode, burst-of-2 uses rising edge of not-K) *Data **Write ***If /WPS is low ****A data word on ''Data In'' is latched on rising edge of K ****The next data word on ''Data In'' is latched on rising edge of /K **Read ***A read is a two-cycle process ***If /RPS is low ****The first rising edge of C latches the read address, A ****The second rising edge of C puts the data word, from address A, on the ''Data Out'' bus ****The next rising edge of /C puts the next data word, from address A+1, on the ''Data Out'' bus

External links

AN4065
QDR-II, QDR-II+, DDR-II, DDR-II+ Design GUide Computer memory