A posted write is a

computer bus In computer architecture, a bus (shortened form of the Latin ''omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This ex ...

write transaction that does not wait for a write completion response to indicate success or failure of the write transaction. For a posted write, the CPU assumes that the write cycle will complete with zero wait states, and so doesn't wait for the done. This speeds up writes considerably. For starters, it doesn't have to wait for the done response, but it also allows for better

pipelining Pipelining may refer to: * Pipeline (computing), aka a data pipeline, a set of data processing elements connected in series ** HTTP pipelining, a technique in which multiple HTTP requests are sent on a single TCP connection ** Instruction pipeli ...

of the

datapath A datapath is a collection of functional units such as arithmetic logic units or multipliers that perform data processing operations, registers, and buses. Along with the control unit it composes the central processing unit (CPU). A larger dat ...

without much performance penalty. A non-posted write requires that a bus transaction responds with a write completion response to indicate success or failure of the transaction, and is naturally much slower than a posted write since it requires a round trip delay similar to read bus transactions. In reference to memory bus accesses, a posted write is referred to as a posted memory write (PMW).

References

PCI System Architecture, Don Anderson, Tom Shanley, MindShare, Inc - 1999

External links

*
Computer hardware buses and slots pinouts with brief descriptions
{{Computer-bus Computer buses Digital electronics Motherboard

See also

References

External links