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Phenom () is the
64-bit In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, a ...
AMD Advanced Micro Devices, Inc. (AMD) is an American multinational corporation and technology company headquartered in Santa Clara, California and maintains significant operations in Austin, Texas. AMD is a hardware and fabless company that de ...
desktop processor line based on the K10 microarchitecture, in what AMD calls family 10h (10 hex, i.e. 16 in normal decimal numbers) processors, sometimes incorrectly called "K10h". Triple-core versions (codenamed ''Toliman'') belong to the Phenom 8000 series and quad cores (codenamed ''Agena'') to the AMD Phenom X4 9000 series. The first processor in the family was released in 2007.


Background

AMD considers the quad core Phenoms to be the first "true" quad core design, as these processors are a monolithic multi-core design (all cores on the same silicon die), unlike Intel's
Core 2 Intel Core 2 is a processor family encompassing a range of Intel's mainstream 64-bit x86-64 single-, dual-, and quad-core microprocessors based on the Core microarchitecture. The single- and dual-core models are single- die, whereas the quad-c ...
Quad series which are a
multi-chip module A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or Lead (electronics), "pins") where multiple integrated circuits (ICs or "chips"), semiconductor Die (integrated circuit), d ...
(MCM) design. The processors are on the
Socket AM2+ Socket AM2+ is a CPU socket, which is the immediate successor to Socket AM2 that is used by several AMD processors such as Athlon 64 X2. Socket AM2+ is a mid-migration from Socket AM2 to Socket AM3 and both AM2+ and AM2 socket CPUs and motherboa ...
platform. Before Phenom's original release a flaw was discovered in the
translation lookaside buffer A translation lookaside buffer (TLB) is a memory CPU cache, cache that stores the recent translations of virtual memory address to a physical memory Memory_address, location. It is used to reduce the time taken to access a user memory location. It ...
(TLB) that could cause a system lock-up in rare circumstances; Phenom processors up to and including stepping "B2" and "BA" are affected by this bug. BIOS and software workarounds disable the TLB, and typically incur a performance penalty of at least 10%. This penalty was not accounted for in pre-release previews of Phenom, hence the performance of early Phenoms delivered to customers may have been less than the preview benchmarks. "B3" stepping Phenom processors were released March 27, 2008 without the TLB bug and with "xx50" model numbers. An AMD subsidiary released a patch for the
Linux kernel The Linux kernel is a Free and open-source software, free and open source Unix-like kernel (operating system), kernel that is used in many computer systems worldwide. The kernel was created by Linus Torvalds in 1991 and was soon adopted as the k ...
, to overcome this bug by software emulation of accessed- and dirty-bits. This method causes less performance loss than previous workarounds. The program was said in December 2007 to have received "minimal functional testing." AMD launched several models of the Phenom processor in 2007 and 2008 and an upgraded
Phenom II Phenom II is a family of AMD's multi-core 45 nm central processing unit, processors using the AMD K10 microarchitecture, succeeding the original AMD Phenom, Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in Dece ...
in late 2008.


Features


Model naming methodology

The model numbers of the Phenom line of processors were changed from the PR system used in its predecessors, the AMD Athlon 64 processor family. The Phenom model numbering scheme, for-later released Athlon X2 processors, is a four-digit model number whose first digit is a family indicator. Energy Efficient products end with an “e” suffix (for example, "Phenom 9350e"). Some Sempron processors use the prefix LE (for example, "Sempron LE-1200")


Cores


Phenom X4


''Agena'' (65 nm SOI)

* Four
AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. The first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops fo ...
cores * L1 cache: 64 KB + 64 KBIn this article, the conventional prefixes for computer memory denote base-2 values whereby “kilobyte” (KB) = 210 bytes. (
data Data ( , ) are a collection of discrete or continuous values that convey information, describing the quantity, quality, fact, statistics, other basic units of meaning, or simply sequences of symbols that may be further interpreted for ...
+ instructions) per core * L2 cache: 512 KB per core, full-speed * L3 cache: 2 MB shared among all cores * Memory controller: dual channel DDR2-1066 MHz with unganging option * MMX, Extended
3DNow! 3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of float ...
, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;
,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new operating modes: 64-bit mode an ...
,
Cool'n'Quiet AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
,
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware- ...
*
Socket AM2+ Socket AM2+ is a CPU socket, which is the immediate successor to Socket AM2 that is used by several AMD processors such as Athlon 64 X2. Socket AM2+ is a mid-migration from Socket AM2 to Socket AM3 and both AM2+ and AM2 socket CPUs and motherboa ...
,
HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer Processor (computing), processors. It is a bidirectional Serial communication, serial/Parallel communication, parallel high-Bandwi ...
with 1600 to 2000 MHz * Power consumption ( TDP): 65, 95, 125 and 140 Watt * First release ** November 19, 2007 (B2 Stepping) ** March 27, 2008 (B3 Stepping) * Clock rate: 1800 to 2600 MHz * Models: Phenom X4 9100e to 9950


Phenom X3


''Toliman'' (65 nm SOI)

* Three
AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. The first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops fo ...
cores chip harvested from Agena with one core disabled * L1 cache: 64 KB
data Data ( , ) are a collection of discrete or continuous values that convey information, describing the quantity, quality, fact, statistics, other basic units of meaning, or simply sequences of symbols that may be further interpreted for ...
and 64 KB instruction cache per core * L2 cache: 512 KB per core, full-speed * L3 cache: 2 MB shared between all cores * Memory controller: dual channel DDR2-1066 MHz with unganging option * MMX, Extended
3DNow! 3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of float ...
, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;
,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new operating modes: 64-bit mode an ...
,
Cool'n'Quiet AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
,
NX bit The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware- ...
*
Socket AM2+ Socket AM2+ is a CPU socket, which is the immediate successor to Socket AM2 that is used by several AMD processors such as Athlon 64 X2. Socket AM2+ is a mid-migration from Socket AM2 to Socket AM3 and both AM2+ and AM2 socket CPUs and motherboa ...
,
HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer Processor (computing), processors. It is a bidirectional Serial communication, serial/Parallel communication, parallel high-Bandwi ...
with 1600 to 1800 MHz * Power consumption ( TDP): 65 and 95 Watt * First release ** March 27, 2008 (B2 Stepping) ** April 23, 2008 (B3 Stepping) * Clock rate: 2100 to 2500 MHz * Models: Phenom X3 8250e to 8850


See also

*
List of AMD Phenom processors The AMD Phenom family is a 64-bit microprocessor family from Advanced Micro Devices (AMD), based on the AMD 10h, K10 microarchitecture. It includes the AMD Phenom II X6 hex-core series, Phenom X4 and Phenom II X4 quad-core series, Phenom X3 and P ...
* List of AMD Athlon X2 processors *
AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. The first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops fo ...


References


External links


AMD Phenom Processor Family
{{DEFAULTSORT:Phenom Computer-related introductions in 2007 AMD x86 microprocessors