The page attribute table (PAT) is a
processor supplementary capability extension to the
page table format of certain
x86 and
x86-64 microprocessors. Like
memory type range registers (MTRRs), they allow for fine-grained control over how areas of memory are
cached, and are a companion feature to the MTRRs.
Unlike MTRRs, which provide the ability to manipulate the behavior of caching for a limited number of fixed physical address ranges, Page Attribute Tables allow for such behavior to be specified on a
per-page basis, greatly increasing the ability of the
operating system to select the most efficient behavior for any given task.
Processors
The PAT is available on
Pentium III and newer CPUs, and on non-Intel CPUs.
See also
*
Write-combining
Write combining (WC) is a computer bus technique for allowing data to be combined and temporarily stored in a buffer the write combine buffer (WCB) to be released together later in burst mode instead of writing (immediately) as single bits or s ...
References
External links
Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1see chapter 11, section 12.
Virtual memory
X86 architecture
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