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OpenSPARC is an
open-source hardware Open-source hardware (OSH, OSHW) consists of physical artifact (software development), artifacts of technology designed and offered by the open-design movement. Both free and open-source software (FOSS) and open-source hardware are created by th ...
project, started in December 2005, for CPUs implementing the SPARC instruction architecture. The initial contribution to the project was
Sun Microsystems Sun Microsystems, Inc., often known as Sun for short, was an American technology company that existed from 1982 to 2010 which developed and sold computers, computer components, software, and information technology services. Sun contributed sig ...
'
register-transfer level In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on th ...
(RTL)
Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the re ...
code for a full
64-bit In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, a ...
, 32- thread
microprocessor A microprocessor is a computer processor (computing), processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, a ...
, the
UltraSPARC T1 The UltraSPARC T1 (codenamed "Niagara") is a Multithreading (computer architecture), multithreading, Multi-core processor, multicore central processing unit, CPU released by Sun Microsystems in 2005. Designed to lower the energy consumption of s ...
processor. On March 21, 2006, Sun released the
source code In computing, source code, or simply code or source, is a plain text computer program written in a programming language. A programmer writes the human readable source code to control the behavior of a computer. Since a computer, at base, only ...
to the T1
IP core IP most often refers to: * Intellectual property, creations of the mind for which exclusive legal rights are recognized * Internet Protocol, a set of rules for sending data across a network IP or Ip or ip may also refer to: Businesses and organi ...
under the
GNU General Public License The GNU General Public Licenses (GNU GPL or simply GPL) are a series of widely used free software licenses, or ''copyleft'' licenses, that guarantee end users the freedom to run, study, share, or modify the software. The GPL was the first ...
v2. The full OpenSPARC T1 system consists of 8 cores, each one capable of executing four threads concurrently, for a total of 32 threads. Each core executes instruction in order and its logic is split among 6 pipeline stages. On December 11, 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project. It was also released under the GNU General public license v2. OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.


See also

* Amber (processor core) – ARM-Compatible OpenCores Project * J Core – SuperH-Compatible OpenCores Project *
LEON Leon, Léon (French) or León (Spanish) may refer to: Places Europe * León, Spain, capital city of the Province of León * Province of León, Spain * Kingdom of León, an independent state in the Iberian Peninsula from 910 to 1230 and again fro ...
*
S1 Core S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the Op ...
(a derived single-core implementation) * FeiTeng, an implementation designed and produced in China for supercomputing applications * Field-programmable gate array *
RISC-V RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project commenced in 2010 at the University of California, Berkeley. It transfer ...


References


External links


OpenSPARC site





Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 (2011)
Article analyzing the law, technology and business of open source semiconductor cores Sun microprocessors Open microprocessors SPARC microprocessors Computer-related introductions in 2005 {{compu-hardware-stub