The
C7 microprocessor from
VIA Technologies
VIA Technologies, Inc. () is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory. It was once the world's largest independent manufacturer of motherboard chipsets. As a fabless semiconductor company, ...
is a seventh-generation CPU targeted at the consumer and embedded market.
Desktop processors
C7
"Esther" (90 nm)
* All models support: ''
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
NX bit
The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)''
*
VIA PowerSaver supported with 2
ACPI
Advanced Configuration and Power Interface (ACPI) is an open standard that operating systems can use to discover and configure computer hardware components, to perform power management (e.g. putting unused hardware components to sleep), auto con ...
P-states
C7-D
"Esther" (90 nm)
* All models support: ''
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
NX bit
The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)''
*
VIA PowerSaver supported on Model D 1.8 and 2.0 with 2
ACPI
Advanced Configuration and Power Interface (ACPI) is an open standard that operating systems can use to discover and configure computer hardware components, to perform power management (e.g. putting unused hardware components to sleep), auto con ...
P-states
Mobile processors
C7-M
"Esther" (standard-voltage, 90 nm)
* All models support: ''
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
NX bit
The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)''
*
VIA PowerSaver supported with up to 8
ACPI
Advanced Configuration and Power Interface (ACPI) is an open standard that operating systems can use to discover and configure computer hardware components, to perform power management (e.g. putting unused hardware components to sleep), auto con ...
P-states
"Esther" (ultra-low-voltage, 90 nm)
* All models support: ''
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
NX bit
The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certai ...
, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)''
*
VIA PowerSaver supported with up to 8
ACPI
Advanced Configuration and Power Interface (ACPI) is an open standard that operating systems can use to discover and configure computer hardware components, to perform power management (e.g. putting unused hardware components to sleep), auto con ...
P-states
External links
VIA C7 product pageVIA C7-D product pageVIA C7-M product page
See also
*
List of VIA microprocessors
This article lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common.
Cyrix design ( Cyrix III)
* All models support: '' MMX, 3DNow!''
Centaur Technology design ...
{{VIA
*C7
VIA