digital logic A logic gate is a device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, one that has, for ...

, a hazard is an undesirable effect caused by either a deficiency in the system or external influences in both

synchronous Synchronization is the coordination of events to operate a system in unison. For example, the conductor of an orchestra keeps the orchestra synchronized or ''in time''. Systems that operate with all parts in synchrony are said to be synchrono ...

and

asynchronous circuit Asynchronous circuit (clockless or self-timed circuit) is a sequential logic, sequential digital logic electrical network, circuit that does not use a global clock circuit or clock signal, signal generator to synchronize its components. Instea ...

s. Logic hazards are manifestations of a problem in which changes in the input variables do not change the output correctly due to some form of delay caused by logic elements ( NOT, AND,

OR gate The OR gate is a digital logic gate that implements logical disjunction. The OR gate outputs "true" if any of its inputs is "true"; otherwise it outputs "false". The input and output states are normally represented by different voltage levels. ...

s, etc.) This results in the logic not performing its function properly. The three different most common kinds of hazards are usually referred to as static, dynamic and function hazards. Hazards are a temporary problem, as the logic circuit will eventually settle to the desired function. Therefore, in synchronous designs, it is standard practice to

register Register or registration may refer to: Arts, entertainment, and media Music * Register (music), the relative "height" or range of a note, melody, part, instrument, etc. * ''Register'', a 2017 album by Travis Miller * Registration (organ), ...

the output of a circuit before it is being used in a different clock domain or routed out of the system, so that hazards do not cause any problems. If that is not the case, however, it is imperative that hazards be eliminated as they can have an effect on other connected systems.

Static hazards

A static hazard is a change of a signal state twice in a row when the signal is expected to stay constant. When one input signal changes, the output changes momentarily before stabilizing to the correct value. There are two types of static hazards: * Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily changes to 0,1 before settling on 1 * Static-0 Hazard: the output is currently 0 and after the inputs change, the output momentarily changes to 1,0 before settling on 0 In properly formed two-level AND-OR logic based on a Sum Of Products expression, there will be no static-0 hazards (but may still have static-1 hazards). Conversely, there will be no static-1 hazards in an OR-AND implementation of a Product Of Sums expression (but may still have static-0 hazards). The most commonly used method to eliminate static hazards is to add redundant logic (consensus terms in the logic expression).

Example of a static hazard

Consider an imperfect circuit that suffers from a delay in the physical logic elements i.e. AND gates etc. The simple circuit performs the function noting: :

\overline = AB  + \overlineC

From a look at the starting diagram it is clear that if no delays were to occur, then the circuit would function normally. However, no two gates are ever manufactured exactly the same. Due to this imperfection, the delay for the first AND gate will be slightly different than its counterpart. Thus an error occurs when the input changes from 111 to 011. i.e. when A changes state. Now we know roughly how the hazard is occurring, for a clearer picture and the solution on how to solve this problem, we would look to the

Karnaugh map A Karnaugh map (KM or K-map) is a diagram that can be used to simplify a Boolean algebra expression. Maurice Karnaugh introduced the technique in 1953 as a refinement of Edward W. Veitch's 1952 Veitch chart, which itself was a rediscovery of ...

. A theorem proved by Huffman tells us that adding a redundant loop 'BC' will eliminate the hazard. The amended function is: :

\overline = AB + \overlineC + BC

Now we can see that even with imperfect logic elements, our example will not show signs of hazards when A changes state. This theory can be applied to any logic system. Computer programs deal with most of this work now, but for simple examples it is quicker to do the debugging by hand. When there are many input variables (say 6 or more) it will become quite difficult to 'see' the errors on a Karnaugh map.

Dynamic hazards

A dynamic hazard are a series of changes of a signal state that happen several times in a row when the signal is expected to change state only once. A dynamic hazard is the possibility of an output changing more than once as a result of a single input change. Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input). If each route has a different delay, then it quickly becomes clear that there is the potential for changing output values that differ from the required / expected output. E.g. A logic circuit is meant to change output state from 1 to 0, but instead changes from 1 to 0 then 1 and finally rests at the correct value 0. This is a dynamic hazard. As a rule, dynamic hazards are more complex to resolve, but note that if all static hazards have been eliminated from a circuit, then dynamic hazards cannot occur.

Functional hazards

In contrast to static and dynamic hazards, functional hazards are ones caused by a change applied to more than one input. There is no specific logical solution to eliminate them. One really reliable method is preventing inputs from changing simultaneously, which is not applicable in some cases. So, circuits should be carefully designed to have equal delays in each path.

Others

; Combinational logic hazards : In

combinational logic In automata theory, combinational logic (also referred to as time-independent logic) is a type of digital logic that is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequ ...

is a hazard that depend on the distribution of

signal propagation delay Propagation delay is the time duration taken for a signal to reach its destination, for example in the electromagnetic field, a wire, gas, fluid or solid body. Physics * An electromagnetic wave travelling through a medium has a propagation ...

s in the logic circuits and overall design of a logic circuit function implemented. ; Combinational functional hazards : In

are hazards that can be detected and suppressed at a higher level of programming, by studying and modifying the output logic function. ; Sequential hazards: Is a kind of undesirable signal changes found in looped systems.

References