A hardware verification language, or HVL, is a programming language used to verify the designs of
electronic circuits written in a
hardware description language. HVLs typically include features of a
high-level programming language like
C++ or
Java as well as features for easy bit-level manipulation similar to those found in
HDLs. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.
SystemVerilog,
OpenVera
OpenVera was a hardware verification language developed by System Science and acquired by Synopsys.
See also
* e (verification language)
* SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware veri ...
,
e, and
SystemC are the most commonly used HVLs.
SystemVerilog attempts to combine HDL and HVL constructs into a single standard.
See also
*
OpenVera
OpenVera was a hardware verification language developed by System Science and acquired by Synopsys.
See also
* e (verification language)
* SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware veri ...
*
e
*
SystemC
*
SystemVerilog
*
Property Specification Language
References
{{compu-lang-stub