An end of interrupt (EOI) is a computing signal sent to a
programmable interrupt controller
In computing, a programmable interrupt controller (PIC) is an integrated circuit that helps a microprocessor (or CPU) handle interrupt requests (IRQs) coming from multiple different sources (like external I/O devices) which may occur simultane ...
(PIC) to indicate the completion of interrupt processing for a given
interrupt
In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted ...
. Interrupts are used to facilitate hardware signals sent to the processor that temporarily stop a running program and allow a special program, an interrupt handler, to run instead. An EOI is used to cause a PIC to clear the corresponding bit in the in-service register (ISR), and thus allow more
interrupt request
In a computer, an interrupt request (or IRQ) is a hardware signal sent to the processor that temporarily stops a running program and allows a special program, an interrupt handler, to run instead. Hardware interrupts are used to handle events s ...
s (IRQs) of equal or lower priority to be generated by the PIC.
EOIs may indicate the
interrupt vector
An interrupt vector table (IVT) is a data structure that associates a list of interrupt handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the addre ...
implicitly or explicitly. An explicit EOI vector is indicated with the EOI, whereas an implicit EOI vector will typically use a vector as indicated by the PICs priority schema, for example the highest vector in the ISR. Also, EOIs may be sent at the end of interrupt processing by an
interrupt handler
In computer systems programming, an interrupt handler, also known as an interrupt service routine (ISR), is a special block of code associated with a specific interrupt condition. Interrupt handlers are initiated by hardware interrupts, software ...
, or the operation of a PIC may be set to auto-EOI at the start of the interrupt handler.
See also
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Intel 8259
The Intel 8259 is a programmable interrupt controller (PIC) designed for the Intel 8085 and Intel 8086, 8086 microprocessors. The initial part was 8259, a later A suffix version was upward compatible and usable with the 8086 or Intel 8088, 8088 ...
– notable PIC from Intel
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Advanced Programmable Interrupt Controller
In computing, Intel's Advanced Programmable Interrupt Controller (APIC) is a family of programmable interrupt controllers. As its name suggests, the APIC is more advanced than Intel's 8259 Programmable Interrupt Controller (PIC), particularly enabl ...
(APIC)
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OpenPIC and IBM MPIC
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Inter-processor interrupt (IPI)
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Interrupt latency
In computing, interrupt latency refers to the delay between the start of an Interrupt Request (IRQ) and the start of the respective Interrupt Service Routine (ISR). For many operating systems, devices are serviced as soon as the device's interru ...
*
Non-maskable interrupt
In computing, a non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore. It typically occurs to signal attention for non-recoverable hardware errors. Some NMIs may be masked, but ...
(NMI)
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IRQL (Windows)
References
Interrupts
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