Duron is a line of budget

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-compatible microprocessors manufactured by

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and released on June 19, 2000. Duron was intended to be a lower-cost offering to complement AMD's then mainstream performance

Athlon AMD Athlon is the brand name applied to a series of x86, x86-compatible microprocessors designed and manufactured by AMD, Advanced Micro Devices. The original Athlon (now called Athlon Classic) was the first seventh-generation x86 processor a ...

processor line, and it also competed with rival chipmaker

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...

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and

Celeron Celeron is a series of IA-32 and x86-64 computer microprocessor, microprocessors targeted at low-cost Personal computer, personal computers, manufactured by Intel from 1998 until 2023. The first Celeron-branded CPU was introduced on April 15, ...

processor offerings. The Duron brand name was retired in 2004, succeeded by AMD's

Sempron Sempron has been the marketing name used by AMD for several different budget desktop CPUs, using several different technologies and CPU socket formats. The Sempron replaced the AMD Duron processor and competed against Intel's Celeron#Celeron D (Pr ...

line of processors as their budget offering.

Performance

The original Duron processors were derived from AMD's mainstream ''Athlon'' Thunderbird processors, the primary difference being a reduction in L2 cache size to 64 KB from the Athlon's 256 KB. This was a relatively severe reduction, making it even smaller than the 128 KB L2 available on Intel's competing budget

line. However, the originating Thunderbird architecture already featured one of the largest L1 caches at 128 KB (which was not reduced in the Duron) and also introduced AMD's switch to an exclusive cache design which effectively unified the L1 and L2 caches. Because of this, the Duron behaved as if it had a high speed 128 KB cache combined with a somewhat slower 64 KB segment giving an effective 192 KB cache, versus the traditional inclusive cache design where the L2 cache had to store a duplicate of the data stored in the L1 cache. As a comparison the inclusive design of the Celeron effectively reduced the available size of the Level 2 cache by the size of the Level 1, which resulted in an effective size of 96 KB (128-32) in contrast to the Duron's exclusive design (128+64=192). Consequently, the Duron inherited the Thunderbird's reduction in sensitivity to L2 cache size, allowing AMD to make their L2 cache higher latency and lower bandwidth to lessen processor complexity and allow better manufacturing yields without incurring a significant performance loss. The net result was that the budget Duron "Spitfire" CPU was roughly only 10% slower than an equivalently clocked (and significantly more expensive) Athlon "Thunderbird".

Compatibility

The Duron line was pin-compatible and operated on the same

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s as the Athlon line, requiring only a BIOS update in most cases. The original Duron was introduced with a 100 MHz (effectively 200 MHz)

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the same as the then current Socket A Athlons. Later with the introduction of motherboard chipsets offering higher FSB speeds of 133 MHz (FSB 266) and AMD's matching introduction of Athlon "C" processors supporting this speed, the Duron initially retained the 100 MHz FSB for purposes of

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. Later Durons were given official support for 133 MHz bus operation only after the Athlon XP was used to introduce 166/200 MHz FSB (FSB 333/400) speeds.

Revisions

The original Duron, using the "Spitfire" core, was manufactured in 2000 and 2001 at speeds ranging from 600 to 950 MHz. It was based on the 180 nm " Thunderbird" Athlon core. The second-generation Duron, the "Morgan" core, was sold in speed grades between 900 and 1300 MHz, and was based on the 180 nm "

Palomino Palomino is a equine coat color, genetic color in horses, consisting of a gold coat and white mane (horse), mane and tail; the degree of whiteness can vary from bright white to yellow. The palomino color derived from the breeding of Spanish hor ...

" Athlon XP core. As a result, it featured a few important enhancements, namely full Intel SSE support, enlarged TLBs, hardware data prefetch, and an integrated thermal diode. Like the "Palomino" core, "Morgan" was also expected to reduce heat dissipation; however in "Morgan"'s case this did not happen due to its increased core voltage. A third-generation Duron, the "Appaloosa" core, was announced in the 2001-2002 AMD Processor Roadmap, to enter production in 2002; this was to be manufactured with AMD's upcoming 130 nm process. Despite rumors of early limited circulation however, "Appaloosa"-based Durons never reached the market, and by the end of 2001, "Appaloosa" had been removed from the roadmap. Instead of the canceled "Appaloosa" core, the Duron line eventually saw a final generation in 2003, in the form of the "Appalbred" core (later typically misspelled as "Applebred"), which was a 130 nm "Thoroughbred" Athlon XP with only 64 KiB (¼) of L2 cache enabled. The name "Appalbred" was a

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of "Appaloosa" and "Thoroughbred", much like the contemporary "Thorton" Athlon XP, a "Barton" with only 256 KiB (½) of L2 cache enabled, was a portmanteau of "Thoroughbred" and "Barton". Neither "Appalbred" nor "Thorton" ever appeared on an official AMD processor roadmap. In the years following its introduction and the withdrawal of the Duron line from the market, the spelling "Appalbred" gradually became replaced by the phonetically similar "Applebred", as "Appaloosa" and the etymology of "Appalbred" were mostly forgotten.

Enthusiasts

Duron was often a favorite of computer builders looking for performance while on a tight budget. In 2003, the "Appalbred" Duron was available in 1.4 GHz, 1.6 GHz and 1.8 GHz grades, all on a 133 MHz (FSB 266) bus. Enthusiast groups quickly discovered these Durons to be rebadged "Thoroughbred B" cores with 192 KiB (¾) of L2 cache disabled and possibly defective. With a basic CPU OPGA package configuration modification, it was found that "Appalbred" Durons could be turned into "Thoroughbred B" Athlon XPs, with full 256 KiB cache, with a very high success rate. However, this was only possible for a period of approximately 4 weeks, as shortly after "Appalbred" was released, AMD made changes to the OPGA package that made these configuration modifications ineffective.

Features

Duron core data

Spitfire (Model 3, 180 nm)

* L1 cache: 64 + 64 KB (Data + Instructions) * L2 cache: 64 KB, full speed * MMX, Extended MMX,

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, Extended 3DNow! *

Socket A Socket A (also known as Socket 462) is a zero insertion force pin grid array (PGA) CPU socket used for AMD processors ranging from the Athlon Thunderbird to the Athlon XP/MP 3200+, and AMD budget processors including the Duron and Sempron. ...

(EV6) *

Front-side bus The front-side bus (FSB) is a computer communication interface ( bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between th ...

: 100 MHz (200 MT/s) * VCore: 1.50 V – 1.60 V * First release: June 19, 2000 *

Clock rate Clock rate or clock speed in computing typically refers to the frequency at which the clock generator of a processor can generate pulses used to synchronize the operations of its components. It is used as an indicator of the processor's s ...

: 600–950 MHz