Compact Model Council

The Compact Model Coalition (formerly the Compact Model Council) is a working group in the electronic design automation (EDA) industry formed to choose, maintain and promote the use of standard semiconductor device models. Commercial and industrial analog simulators (such as SPICE) need to add device models as technology advances (see Moore's law) and earlier models become inaccurate. Before this group was formed, new transistor models were largely proprietary, which severely limited the choice of simulators that could be used.

It was formed in August, 1996, for the purpose developing and standardizing the use and implementation of SPICE models and the model interfaces. In May 2013, the Silicon Integration Initiative (Si2) and TechAmerica announced the transfer of the Compact Model Council to Si2 and a renaming to Compact Model Coalition.

To develop and maintain the models, the CMC works with device modeling and simulation experts belonging to an international collection of universities and research institutions.   In alphabetical order, the present development organizations are Auburn University (SiGe group), CEA-LETI, Hiroshima University (HiSIM Research Center), Macquarie University, TU Dresden (HiCUM development), UC Berkeley (BSIM Group), and University of Waterloo (WEIS Group).   Though the development is done at these different institutions, all of them follow the same Verilog-A coding standards and QA standards, and they all go through a common beta testing and release process.  CMC maintains a workgroup for each standardized model, composed of interested industry members and the model developers.

Most of the CMC development is industry-funded, supported by dues from CMC member companies.  The member companies primarily are silicon design companies, silicon foundry companies, Integrated Device Manufacturers (IDM), and silicon design EDA companies.

Production releases of industry-funded CMC models are available to the public free of charge.  The CMC member companies have access to earlier pre-production versions of those models, and they have the opportunity to help direct the evolution of those models.

The industry-funded CMC models, listed alphabetically,  are:

*

To address the increasing need for Reliability (ageing) simulation the CMC nominated the OMI Interface as the new EDA vendor independent solution for ageing simulations. Technically the Interface is very close the TMI2 Interface developed by TSMC. The standardization will allow Silicon Foundries to develop a common set of aging models that will work with all significant analog simulators.

The CMC also has released a Verilog-A code recommended best practices document (“CMC Policy on Standardization of Verilog-A Model Code”) and a Verilog-A Linter program called VAMPyR
(Github link)
which can be freely accessed to help increase the quality of model code for all model developers worldwide.

The CMC continues to evaluate new models for standardarization.  New models are submitted to the Coalition, where their technical merits are discussed, and then potential standard models are voted on.

In 2025, the CMC has started a new initiative and is setting up and running the first International Compact Modeling Conference (ICMC), to be held on June 26-June 27 in San Francisco, co-located with the DAC 2025 conference.

See also

* Electronic circuit simulation

References

{{Reflist

External links

Member list at CMC website

Site map of CMC website including links to working groups

Transistor modeling
Electronic engineering