A chip scale package or chip-scale package (CSP) is a type of integrated circuit package. Originally, CSP was the acronym for ''chip-size packaging.'' Since only a few packages are chip size, the meaning of the acronym was adapted to ''chip-scale packaging''. According to

IPC IPC may refer to: Computing * Infrastructure protection centre or information security operations center * Instructions per cycle or instructions per clock, an aspect of central-processing performance * Inter-process communication, the sharin ...

's standard J-STD-012, ''Implementation of Flip Chip and Chip Scale Technology'', in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm. The concept was first proposed by Junichi Kasai of

Fujitsu is a Japanese multinational information and communications technology equipment and services corporation, established in 1935 and headquartered in Tokyo. Fujitsu is the world's sixth-largest IT services provider by annual revenue, and the la ...

and Gen Murakami of

Hitachi Cable was established in 1956 as a manufacturer of electric wire and cable for power distribution. The company, based in Tokyo, Japan, was formed from Hitachi Densen Works, the Hitachi Works spin-off previously known as Densen Works. In the half-centu ...

in 1993. The first concept demonstration however came from

Mitsubishi Electric , established on 15 January 1921, is a Japanese multinational electronics and electrical equipment manufacturing company headquartered in Tokyo, Japan. It is one of the core companies of Mitsubishi. The products from MELCO include elevators a ...

. The die may be mounted on an

interposer An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection. Interposer comes from t ...

upon which pads or balls are formed, like with

flip chip Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to extern ...

ball grid array A ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put ...

(BGA) packaging, or the pads may be etched or printed directly onto the

silicon wafer In electronics, a wafer (also called a slice or substrate) is a thin slice of semiconductor, such as a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells. The wafer ser ...

, resulting in a package very close to the size of the silicon die: such a package is called a

wafer-level package Wafer-level packaging (WLP) is a process where packaging components are attached to an integrated circuit (IC) ''before'' the wafer – on which the IC is fabricated – is diced. In WSP, the top and bottom layers of the packaging and the sold ...

(WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as

Advanced Semiconductor Engineering Advanced Semiconductor Engineering, Inc. (), also known as ASE Group (), is a provider of independent semiconductor assembling and test manufacturing services, with its headquarters in Kaohsiung, Taiwan. Overview The company was founded in 1984 ...

(ASE).

Types

Chip scale packages can be classified into the following groups: # Customized leadframe-based CSP (LFCSP) # Flexible substrate-based CSP # Flip-chip CSP (FCCSP) # Rigid substrate-based CSP # Wafer-level redistribution CSP (WL-CSP)

References

External links

Definition
by

JEDEC The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States. JEDEC has over 300 members, including some of the w ...

The Nordic Electronics Packaging Guideline, Chapter D: Chip Scale Packaging
* {{electronics-stub