In
computer architecture, bit-serial architectures send data one bit at a time, along a single wire, in contrast to
bit-parallel word
A word is a basic element of language that carries semantics, meaning, can be used on its own, and is uninterruptible. Despite the fact that language speakers often have an intuitive grasp of what a word is, there is no consensus among linguist ...
architectures, in which data values are sent all bits or a word at once along a group of wires.
All digital computers built before 1951, and most of the early
massive parallel processing machines used a bit-serial architecture—they were
serial computer
A serial computer is a computer typified by bit-serial architecture i.e., internally operating on one bit or numerical digit, digit for each clock signal, clock cycle. Machines with serial main storage devices such as acoustic or magnetostrictive ...
s.
Bit-serial architectures were developed for
digital signal processing
Digital signal processing (DSP) is the use of digital processing, such as by computers or more specialized digital signal processors, to perform a wide variety of signal processing operations. The digital signals processed in this manner are a ...
in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.
The
HP Nut processor used in many
Hewlett-Packard calculators operated bit-serially.
Assuming N is an arbitrary integer number, N serial processors will often take less
FPGA area and have a higher total performance than a single N-bit parallel processor.
See also
*
Serial computer
A serial computer is a computer typified by bit-serial architecture i.e., internally operating on one bit or numerical digit, digit for each clock signal, clock cycle. Machines with serial main storage devices such as acoustic or magnetostrictive ...
*
1-bit computing
*
Bit banging
*
Bit slicing
*
BKM algorithm
*
CORDIC
References
External links
Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method BIT-Serial FIR filters with CSD Coefficients for FPGAs
Data transmission
{{comp-sci-stub