Advanced Synchronization Facility (ASF) is a proposed extension to the
x86-64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging ...
instruction set architecture
In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ...
that adds hardware
transactional memory support. It was introduced by
AMD; the latest specification was dated March 2009.
, it was still in the proposal stage.
No released
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
s implement the extension.
Features
ASF provides the capability to start, end and abort transactional execution and to mark
CPU
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and ...
cache lines for protected memory access in transactional code regions. It contains four new instructions—
SPECULATE,
COMMIT,
ABORT and
RELEASE—and turns the otherwise invalid
LOCK-prefixed
MOVx,
PREFETCH and
PREFETCHW instructions into valid ones inside transactional code regions. Up to 256 levels of nested transactional code regions is supported.
The
SPECULATE and
COMMIT instructions mark the start and end of a transactional code region. Inside transactional code regions, the
LOCK-prefixed
MOVx reg/xmm, mem,
PREFETCH and
PREFETCHW instructions can mark up to four cache lines for protected memory access. Accesses from other processor cores to the protected cache lines result in exceptions, which in turn cause transaction aborts. Stores to protected cache lines must be performed using the
LOCK MOVx mem, reg/imm/xmm instructions. Marked cache lines can be released from protection with the
RELEASE instruction. Transaction aborts generated by hardware or explicitly requested through the
ABORT instruction rolls back modifications to the protected cache lines and restarts execution from the instruction following the top-level
SPECULATE instruction.
See also
*
Transactional Synchronization Extensions
Transactional Synchronization Extensions (TSX), also called Transactional Synchronization Extensions New Instructions (TSX-NI), is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory support, speeding ...
, Intel's competing technology first implemented in Haswell-based microprocessors
References
{{Multimedia extensions, state=uncollapsed
X86 instructions
Parallel computing
Transactional memory
Transaction processing
Concurrency control
AMD technologies