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The Puma Family 16h is a low-power
microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be impl ...
by AMD for its APUs. It succeeds the
Jaguar The jaguar (''Panthera onca'') is a large cat species and the only living member of the genus '' Panthera'' native to the Americas. With a body length of up to and a weight of up to , it is the largest cat species in the Americas and the th ...
as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The ''Beema'' line of processors are aimed at low-power notebooks, and ''Mullins'' are targeting the tablet sector.


Design

The Puma cores use the same microarchitecture as Jaguar, and inherits the design: *
Out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a proce ...
and Speculative execution, up to 4 CPU cores * Two-way integer execution * Two-way 128-bit wide floating-point and packed integer execution * Integer hardware divider * Puma does not feature
clustered multi-thread The AMD Bulldozer Family 15h is a microprocessor microarchitecture for the FX and Opteron line of processors, developed by AMD for the desktop and server markets. Bulldozer is the codename for this family of microarchitectures. It was released o ...
(CMT), meaning that there are no "modules" * Puma does not feature Heterogeneous System Architecture or zero-copy * 32 KiB instruction + 32 KiB data L1 cache per core * 1–2 MiB unified L2 cache shared by two or four cores * Integrated single channel memory controller supporting 64bit DDR3L * 3.1 mm2 area per core


Instruction set support

Like Jaguar, the ''Puma'' core has support for the following instruction sets and instructions: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT,
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ac ...
(POPCNT/LZCNT), and
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
.


Improvements over ''Jaguar''

* 19% CPU core leakage reduction at 1.2V * 38% GPU leakage reduction * 500 mW reduction in memory controller power * 200 mW reduction in display interface power * Chassis temperature aware turbo boost * Selective boosting according to application needs (intelligent boost) * Support for ARM TrustZone via integrated
Cortex-A5 The ARM Cortex-A5 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2009. Overview The Cortex-A5 is intended to replace the ARM9 and ARM11 cores for use in low-end devices. The Cortex-A5 off ...
processor * Support for DDR3L-1866 memory


Puma+

AMD released a revision of Puma microarchitecture, Puma+, updating the video decoder from UVD 4.2 to 6.0 and the video encoder from VCE 2.0 to VCE 3.1.


Features

APU features table


Processors


Desktop/Mobile (Beema)


Tablet (Mullins)


References


External links


Software Optimization Guide for Family 16h Processors

2014 AMD Low-Power Mobile APUs

Jaguar presentation (video)
at ISSCC 2013
Discussion initiated on RWT forums by Jeff Rupley, Chief Architect of the Jaguar core

BKDG for Family 16h Models 00h-0Fh Processors

Revision Guide for Family 16h Models 00h-0Fh Processors
(Jaguar)
Revision Guide for Family 16h Models 30h-3Fh Processors
(Puma) {{Single-board computer AMD x86 microprocessors AMD microarchitectures